tracking the rising_edge of 2 clocks

process (clk,clks)

if (rising_edge (clk)) and rising_edge (clks)) then 

 pout <= 1;
else 
pout <= '0';

process (clk,clks)
begin 

if (rising_edge (clk)and(rising_edge (clks) )) then 

counter1 <= "0000001";
else 
counter1 <= "0000000"; 
end if ;

end process;



packetouts(6 downto 0) <= counter1;

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:32:10 11/07/2016
-- Design Name:   rom
-- Module Name:   C:/payel/vhdltestbench.vhd
-- Project Name:  payel
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: rom
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY vhdltestbench_vhd IS
END vhdltestbench_vhd;

ARCHITECTURE behavior OF vhdltestbench_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT rom
	PORT(
		clk : IN std_logic;
		clks : IN std_logic;
		reset : IN std_logic;          
		firstout : OUT integer;
		dout : OUT std_logic_vector(21 downto 0);
		yout : OUT std_logic_vector(8 downto 0);
		youts : OUT std_logic_vector(8 downto 0);
		packetoutput : OUT std_logic_vector(21 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL clks :  std_logic := '0';
	SIGNAL reset :  std_logic := '1';

	--Outputs
	SIGNAL firstout :  integer;
	SIGNAL dout :  std_logic_vector(21 downto 0);
	SIGNAL yout :  std_logic_vector(8 downto 0);
	SIGNAL youts :  std_logic_vector(8 downto 0);
	SIGNAL packetoutput :  std_logic_vector(21 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: rom PORT MAP(
		clk => clk,
		clks => clks,
		firstout => firstout,
		dout => dout,
		reset => reset,
		yout => yout,
		youts => youts,
		packetoutput => packetoutput
	);

	

	tb : PROCESS
	BEGIN
clk <= '0';
	
	
wait for 1 ns;
clk <= '1';

wait for 1 ns;

reset <= '0';
	END PROCESS;
	
	
	
	
	process
	
	begin
	
	clks <= '0'; 
wait for 2 ns;
clks <= '1'; 
wait for 1 ns;


	
	END PROCESS;

END;

process (clk,clks)
begin 
  if ([COLOR="#FF0000"][B][I]rising_edge (clk)and(rising_edge (clks) )[/I][/B][/COLOR]) then 
    counter1 <= "0000001";
  else 
    counter1 <= "0000000"; 
  end if ;
end process;
packetouts(6 downto 0) <= counter1;