Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PSS does not converge

Status
Not open for further replies.
S

Saraadib

Member level 4
Joined
Nov 2, 2015
Messages
78
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
1,116
Hi everyone
I design clock generator that create four non overlap clock at 1 GHZ,in fact I have four non overlap clock which each one has frequency of 1Ghz
I can do transient analysis and it gives me four non overlap clock at 1Ghz,however when I do PSS analysis I got converge problem,it said it does not converge .
I change tstab and some parameter but still give me this error
anybody have any idea?
Thanks in advance
 

This is my netlist :
Code: 
// Generated on: Oct 26 19:23:32 2016

// Design view name: schematic
simulator lang=spectre
global 0
parameters vdd=1.6
include "/CMC/kits/IBM_PDK/cmrf8sf/relDM/Spectre/models/design.scs"
include "/CMC/kits/IBM_PDK/cmrf8sf/relDM/Spectre/models/allModels.scs" section=tt

// Library name: clockgenerator_layoutRFtransistor
// Cell name: norgate_test
// View name: schematic
subckt norgate_test A B OUT gnd vdd
    T0 (OUT A gnd gnd) nfet_rf l=120.0n w=1.59u nf=3 m=1 par=1 ngcon=1 \
        ad=2.438e-13 as=4.823e-13 pd=2.51u ps=3.94u nrd=0.1132 nrs=0.1132 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T1 (OUT B gnd gnd) nfet_rf l=120.0n w=1.59u nf=3 m=1 par=1 ngcon=1 \
        ad=2.438e-13 as=4.823e-13 pd=2.51u ps=3.94u nrd=0.1132 nrs=0.1132 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T2 (OUT B net43 vdd) pfet_rf l=120.0n w=4.8u nf=3 m=1 par=1 ngcon=1 \
        ad=7.36e-13 as=1.456e-12 pd=5.72u ps=8.22u nrd=0.0375 nrs=0.0375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T3 (net43 A vdd vdd) pfet_rf l=120.0n w=4.8u nf=3 m=1 par=1 ngcon=1 \
        ad=7.36e-13 as=1.456e-12 pd=5.72u ps=8.22u nrd=0.0375 nrs=0.0375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends norgate_test
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: buffer5x
// View name: schematic
subckt buffer5x gnd _net0 _net1 vdd
    T4 (net7 _net0 gnd gnd) nfet_rf l=120.0n w=8u nf=4 m=1 par=1 ngcon=1 \
        ad=1.44e-12 as=2.02e-12 pd=9.44u ps=12.02u nrd=0.0225 nrs=0.0225 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T5 (_net1 net7 gnd gnd) nfet_rf l=120.0n w=8u nf=4 m=1 par=1 ngcon=1 \
        ad=1.44e-12 as=2.02e-12 pd=9.44u ps=12.02u nrd=0.0225 nrs=0.0225 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T0 (net7 _net0 vdd vdd) pfet_rf l=120.0n w=24.0u nf=12 m=1 par=1 \
        ngcon=1 ad=4.32e-12 as=4.9e-12 pd=28.32u ps=30.9u nrd=0.0075 \
        nrs=0.0075 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
    T2 (_net1 net7 vdd vdd) pfet_rf l=120.0n w=24.0u nf=12 m=1 par=1 \
        ngcon=1 ad=4.32e-12 as=4.9e-12 pd=28.32u ps=30.9u nrd=0.0075 \
        nrs=0.0075 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
ends buffer5x
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: buffer1x
// View name: schematic
subckt buffer1x gnd _net3 _net2 vdd
    T1 (_net2 net7 gnd gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T0 (net7 _net3 gnd gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T4 (net7 _net3 vdd vdd) pfet_rf l=120.0n w=4.8u nf=3 m=1 par=1 ngcon=1 \
        ad=7.36e-13 as=1.456e-12 pd=5.72u ps=8.22u nrd=0.0375 nrs=0.0375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T5 (_net2 net7 vdd vdd) pfet_rf l=120.0n w=4.8u nf=3 m=1 par=1 ngcon=1 \
        ad=7.36e-13 as=1.456e-12 pd=5.72u ps=8.22u nrd=0.0375 nrs=0.0375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends buffer1x
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: buffer25x_new
// View name: schematic
subckt buffer25x_new gnd _net5 _net4 vdd
    T3 (_net4 middle gnd gnd) nfet_rf l=120.0n w=40u nf=20 m=1 par=1 \
        ngcon=1 ad=7.2e-12 as=7.78e-12 pd=47.2u ps=49.78u nrd=0.0045 \
        nrs=0.0045 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
    T1 (middle _net5 gnd gnd) nfet_rf l=120.0n w=40u nf=20 m=1 par=1 \
        ngcon=1 ad=7.2e-12 as=7.78e-12 pd=47.2u ps=49.78u nrd=0.0045 \
        nrs=0.0045 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
    T2 (_net4 middle vdd vdd) pfet_rf l=120.0n w=40u nf=20 m=3 par=3 \
        ngcon=1 ad=7.2e-12 as=7.78e-12 pd=47.2u ps=49.78u nrd=0.0045 \
        nrs=0.0045 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
    T0 (middle _net5 vdd vdd) pfet_rf l=120.0n w=40u nf=20 m=3 par=3 \
        ngcon=1 ad=7.2e-12 as=7.78e-12 pd=47.2u ps=49.78u nrd=0.0045 \
        nrs=0.0045 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 \
        lstis=1 lnws=0 rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 \
        panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p \
        panw8=0p panw9=0p panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 \
        dtemp=0
ends buffer25x_new
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: buffer1x_5x_25x
// View name: schematic
subckt buffer1x_5x_25x buffers_in gnd out1 vdd
    I183 (gnd net21 net20 vdd) buffer5x
    I184 (gnd buffers_in net21 vdd) buffer1x
    I0 (gnd net20 out1 vdd) buffer25x_new
ends buffer1x_5x_25x
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: invertor1
// View name: schematic
subckt invertor1 gnd in out vdd
    T2 (out in vdd vdd) pfet_rf l=120.0n w=4.8u nf=3 m=1 par=1 ngcon=1 \
        ad=7.36e-13 as=1.456e-12 pd=5.72u ps=8.22u nrd=0.0375 nrs=0.0375 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T3 (out in gnd gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends invertor1
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: transmissiongate2
// View name: schematic
subckt transmissiongate2 clck clckbar gnd in out vdd
    T2 (in clckbar out vdd) pfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T1 (in clck out gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends transmissiongate2
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: Transmissiongate
// View name: schematic
subckt Transmissiongate clck clckbar gnd in out vdd
    T2 (in clckbar out vdd) pfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T1 (in clck out gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends Transmissiongate
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: Flipflop
// View name: schematic
subckt Flipflop clck gnd in out vdd
    I4 (gnd net014 net80 vdd) invertor1
    I7 (gnd net80 out vdd) invertor1
    I12 (gnd clck net016 vdd) invertor1
    I3 (gnd net015 net76 vdd) invertor1
    I2 (gnd clck clckbar vdd) invertor1
    I1 (gnd in net06 vdd) invertor1
    I9 (net016 clck gnd net76 net014 vdd) transmissiongate2
    I0 (clck clckbar gnd net06 net015 vdd) Transmissiongate
ends Flipflop
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: inverter2
// View name: schematic
subckt inverter2 gnd in out vdd
    T2 (out in vdd vdd) pfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
    T3 (out in gnd gnd) nfet_rf l=120.0n w=1.6u nf=2 m=1 par=1 ngcon=1 \
        ad=2.88e-13 as=5.2e-13 pd=2.32u ps=3.7u nrd=0.1125 nrs=0.1125 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=3 rbodymod=1 gtab=1 ring=2 cwire=1 panw1=0p panw2=0p \
        panw3=0p panw4=0p panw5=0p panw6=0p panw7=0p panw8=0p panw9=0p \
        panw10=0p sa=5.5e-07 sb=5.5e-07 sd=3.6e-07 dtemp=0
ends inverter2
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: inverte1and2
// View name: schematic
subckt inverte1and2 gnd in out vdd
    I187 (gnd net14 out vdd) inverter2
    I188 (gnd in net14 vdd) invertor1
ends inverte1and2
// End of subcircuit definition.

// Library name: clockgenerator_layoutRFtransistor
// Cell name: inverte1and2_2
// View name: schematic
subckt inverte1and2_2 gnd in out vdd
    I213 (gnd net23 out vdd) inverte1and2
    I217 (gnd in net23 vdd) inverte1and2
ends inverte1and2_2
// End of subcircuit definition.

// Library name: finalshematic
// Cell name: clcokgeneratorFianlFinal
// View name: schematic
subckt clcokgeneratorFianlFinal 1 2 3 FFout1 FFout2 FFout3 FFout4 C clck \
        gnd out1 out2 out3 out4 vdd
    I208 (3 2 C gnd vdd) norgate_test
    I212 (net043 gnd out4 vdd) buffer1x_5x_25x
    I210 (18 gnd out2 vdd) buffer1x_5x_25x
    I209 (net044 gnd out1 vdd) buffer1x_5x_25x
    I211 (net0129 gnd out3 vdd) buffer1x_5x_25x
    I207 (clck gnd 2 3 vdd) Flipflop
    I205 (clck gnd FFout3 FFout4 vdd) Flipflop
    I204 (clck gnd FFout2 FFout3 vdd) Flipflop
    I203 (clck gnd FFout1 FFout2 vdd) Flipflop
    I202 (clck gnd C FFout1 vdd) Flipflop
    I171 (clck gnd 1 2 vdd) Flipflop
    I221 (gnd FFout1 net044 vdd) inverte1and2_2
    I224 (gnd FFout4 net043 vdd) inverte1and2_2
    I222 (gnd FFout2 18 vdd) inverte1and2_2
    I223 (gnd FFout3 net0129 vdd) inverte1and2_2
    I139 (gnd 3 1 vdd) invertor1
ends clcokgeneratorFianlFinal
// End of subcircuit definition.

// Library name: finalshematic_Backup
// Cell name: clcokgeneratorFianlFinal_test
// View name: schematic
I26 (1 2 3 ffout1 ffout2 ffout3 ffout4 norout1 net1 0 out1 out2 out3 out4 \
        net017) clcokgeneratorFianlFinal
C5 (out3 0) capacitor c=600f
C6 (out2 0) capacitor c=600f
C7 (out1 0) capacitor c=600f
C4 (out4 0) capacitor c=600f
V2 (net017 0) vsource dc=vdd type=dc
V0 (net1 0) vsource type=pulse val0=0 val1=vdd period=250p delay=0 \
        rise=25p fall=25p width=100p
nodeset out3=0 out4=0 net1=0 
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=0.5e-12 rforce=1 diagnose=yes \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf 
pss  pss  fund=4G  harms=3  errpreset=conservative  tstab=40n
+    maxstep=5p  method=gear2only  annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=all pwr=all currents=all subcktprobelvl=10 \
    useprobes=yes
 

Maybe you could try to increase your tstab time. It works for me sometimes.
And if this does not work, there is an option in ADEL -> simulation -> options -> analog -> check, enable "diagnose", then run your simulation again. in your log file, you can try to find out what is the root cause for the convergence problem
 

You didn't attached a simulation log with mentioned error, but based on netlist I could suggest to add a following options:
try_fast_op=no, dc_pivot_check=yes, pivotdc=yes and change pivrel to 0.1. All above You are able to click in simulation→analog options.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top