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Why does I2S have extra clock cycle in SCLK that is wasted?

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matrixofdynamism

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It seems that there is normal I2S, left justified I2S and right justified I2S. The left and right justified make sense. However, the normal I2S has something peculiar about it.

Once the LRCK changes polarity, the value of SDATA on the first rising edge of SCLK seems to be ignored. Is this a mistake in the datasheet? Why is this done? The image is below with the questioned part circled red.

normal i2s.png

Is this a mistake in the datasheet of CS4334? I looked into the "TAS3004 Digital Audio Processor with Codec" data manual page 2-6 and it showed an X for the first bit.
 

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