Adnan86
Full Member level 2
hi
I write this 2 codes for 4 bits counter. main and testbench
and testbench
but my output in simulation not change. i dont know why.
I will be appreciate if someone help.
- - - Updated - - -
plus i used ise xilinx.
I write this 2 codes for 4 bits counter. main and testbench
Code:
module counter4 (input reset, clk,
output reg [3:0] count );
//reg [3:0] count;
always @ (negedge clk) begin
if (reset) count <= #3 4'b00_00;
else count <= #5 count + 1;
end
endmodule
and testbench
Code:
module test_counter;
// Inputs
reg reset;
reg clk;
// Outputs
wire [3:0] count = 4'b0000;
// Instantiate the Unit Under Test (UUT)
counter4 uut (
.reset(reset),
.clk(clk),
.count(count)
);
always
begin
#20 clk = ~clk;
end
initial begin
// Initialize Inputs
reset = 0; clk = 0;
#30 reset = 1;
#30 reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
but my output in simulation not change. i dont know why.
I will be appreciate if someone help.
- - - Updated - - -
plus i used ise xilinx.