Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

verilog : help for counter

Status
Not open for further replies.
A

Adnan86

Full Member level 2
Joined
Apr 4, 2013
Messages
121
Helped
26
Reputation
52
Reaction score
26
Trophy points
1,308
Activity points
2,153
hi
I write this 2 codes for 4 bits counter. main and testbench
Code: 
module counter4 (input reset, clk,
                 output  reg [3:0] count );
					  //reg  [3:0] count;
                  
    always @ (negedge clk) begin
        if (reset)   count <= #3 4'b00_00;
        else			count <= #5 count + 1;
    end
endmodule

and testbench
Code: 
module test_counter;

	// Inputs
	reg reset;
	reg clk;

	// Outputs
	wire   [3:0] count = 4'b0000;

	// Instantiate the Unit Under Test (UUT)
	counter4 uut (
		.reset(reset), 
		.clk(clk), 
		.count(count)
	);
	always
	begin
	#20	clk = ~clk;
	end
	initial begin
		// Initialize Inputs
		reset = 0; clk = 0;
		#30 reset = 1;
		#30 reset = 0;
	
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

but my output in simulation not change. i dont know why.
I will be appreciate if someone help.

- - - Updated - - -

plus i used ise xilinx.
 

You have a race condition releasing reset. Make sure reset is active during a posedge of clk
 
dave_59 said:
You have a race condition releasing reset. Make sure reset is active during a posedge of clk
Click to expand...

reset work correctly. output after rest show unknown number like( x ).
When reset active, output is 0, but after that output = x;
 

Hi

you have a mistake in test bench

Code: 
// Outputs
	wire   [3:0] count = 4'b0000;

you can't set initial value to wire that is used as output of a module;
correct that as :
Code: 
// Outputs
	wire   [3:0] count ;

enjoy!
 
hamidmoallemi said:
Hi

you have a mistake in test bench

Code: 
// Outputs
	wire   [3:0] count = 4'b0000;

you can't set initial value to wire that is used as output of a module;
correct that as :
Code: 
// Outputs
	wire   [3:0] count ;

enjoy!
Click to expand...

Thanks my friends. My problem solved.
I didnt know that i cant set initial value to wire.
 

If you put an initial value on a wire and I'm pretty sure you'll end up with X's on the signal.

I suggest you leave out # delays in behavioral HDL code namely the UUT you have a #3 in the reset and #5 in the count assignment. They will just generate more warnings from synthesis tools when they are ignored and when you have a engineering job you won't find them in others code, so adding them in your code to see that signal transitions occur after clock edges, won't help you when using others code. Get used to not having the delays now and you'll be better off.
 
ads-ee said:
If you put an initial value on a wire and I'm pretty sure you'll end up with X's on the signal.

I suggest you leave out # delays in behavioral HDL code namely the UUT you have a #3 in the reset and #5 in the count assignment. They will just generate more warnings from synthesis tools when they are ignored and when you have a engineering job you won't find them in others code, so adding them in your code to see that signal transitions occur after clock edges, won't help you when using others code. Get used to not having the delays now and you'll be better off.
Click to expand...
Thanks for you advice. I used this code from Verilog digital system design book by Prof. Navabi. He used delay in codes.
But you right, I always have warning for DELAYs with this message that system ignore them. but, if i have to use delay, what can i do. Do you have any advice ?
I appreciate for your kind answer.

- - - Updated - - -
 

Delays in synthesizable code should be avoided.

Delays in non-synthesizable code (i.e. testbenches) are fine as you typically won't synthesize a testbench and will likely use many non-synthesizable code in a testbench (i.e. things like directly accessing internal nodes in a UUT to know when to start your test, like monitoring the release of an internal reset generator uut.reset_block.internal_reset_signal)

As a # delay is not realizable in hardware, you should be timing things based on clocks and counters for longer periods of time.
 

I still believe you have not held reset active long enough in your testbench. Your clock period is 40 and you only assert reset for 30. Your de-assert of reset coincides with a posedge of clk. This race may work for you sometimes, and fail other times. Move the reset = 0 away from the coincident edge, or use a non-blocking assignment.
 

The OP is using a negedge clock.

So the timing looks like this
Code: 
  10  20  30  40  50  60  
       _______         ___
______|       |_______|   
           ___________
__________|           |___
              ^ Reset takes effect here

Which means the reset is seen as it needs a falling edge clock and is not on the clock edge. If the OP posted incorrect code and they did use a posedge clock then the race condition may apply.
 

Thanks for all kind answers .
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top