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3-Stage Filter wit 1 Bit Input for a Delta-Sigma Modulator (MATLAB->VHDL)

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hyperbolicus

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Hello,


I’ve got problem with my 3 Stage Filter Design in MATLAB (for a Delta-Sigma Modulator),
it would be great if someone could help!

The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz.
So I decided to do a 3 stage Filter: CIC w. 1 Bit input (decimation factor R = 128), CIC Compensator and a polyphase FIR (both have R = 2). The specs of the stages were done according to Hagenauer paper (hopefully correctly).

I also fixed the input of the CIC stage to 1 bit via step(...) function, because in dsp.CICDecimator MATLAB function there are no options to set up the input word length (unlike it was in no longer supported mfilt. function).

Here is my MATLAB code:

Code:
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%CASCADE of a CIC Desimation Filter and a (polyphase) FIR
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% CIC Filter specifications
D = 1; % Differential delays in the filter.
Nsecs = 4; % Filter sections
R = 128; % Decimation factor
iwl = 1; %input word length
%owl = 26;%output word length

hcic = dsp.CICDecimator('DecimationFactor',R,'DifferentialDelay',D,'NumSections',Nsecs); %
% lock object with desired input
step(hcic , fi(zeros(128,1),0,1,0));
info(hcic)

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%plot and analyze the theoretical magnitude response of the CIC filter
Fs_in = 1e6;
h2 = fvtool(hcic,'Fs',Fs_in);
h2.Color = 'White';


%Normalizing the CIC filter response to have 0 dB gain at DC 
h2.NormalizeMagnitudeto1 = 'on';


%the CIC has about -0.xx dB of attenuation (droop) at xx Hz, 
%which is within the bandwidth of interest. 
%A CIC filter is essentially a cascade of boxcar filters and therefore has a sinc-like response 
%which causes the droop. This droop needs to be compensated by the FIR filter in the next stage.

%axis([0 2 -2 0]);

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

% FIR Filter specifications
Fs     = 8e3; % Sampling frequency 1024kHz/128
Apass  = 0.1;     % dB
Astop  = 100;       % dB
Fpass  = 1e3;     % Hz passband-edge frequency
Fstop  = 2e3;    % Hz stopband-edge frequency

% Design decimation filter. D and Nsecs have been defined above as the
% differential delay and number of sections, respectively.
hcfir = dsp.CICCompensationDecimator('SampleRate',Fs,...
    'CICRateChangeFactor',R,'CICNumSections',Nsecs,...
    'CICDifferentialDelay',D,'PassbandFrequency',Fpass,...
    'StopbandFrequency',Fstop,'PassbandRipple',Apass,...
    'StopbandAttenuation',Astop);


info(hcfir)

%Cascading the CIC with the inverse sinc filter we can see if we eliminated 
%the passband droop caused by the CIC.

hcas1 = cascade(hcic,hcfir);
h2 = fvtool(hcic,hcfir,hcas1,'Fs',[Fs_in,Fs_in/128,Fs_in]);
h2.Color = 'White';
h2.NormalizeMagnitudeto1 = 'on';
%axis([0 2 -2 0.8]);
legend(h2,'hcic','hcfir','cascade');

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

N = 29;       % 30 taps
Fs = 4e3;  % 4 kHz
Fpass = 1e3;
Fstop = 1.6e3;

d = fdesign.decimator(2,'lowpass','N,Fp,Fst',N,Fpass,Fstop,Fs);
% Give more weight to passband
hpfir = design(d,'equiripple','Wpass',2,'SystemObject',true);


hpfir.FullPrecisionOverride = false;
hpfir.OutputDataType = 'custom';
hpfir.RoundingMethod = 'nearest';
hpfir.OverflowAction = 'Saturate';
hpfir.CustomOutputDataType = numerictype([],29,-12);
%We can use the info method to view the filter details.

info(hpfir)

hcas = cascade(hcic,hcfir,hpfir);
h3 = fvtool(hcas,'Fs',Fs_in);
h3.Color = 'White';
h3.NormalizeMagnitudeto1 = 'on';
h3.NumberofPoints = 8192*3;
axis([0 50 -250 50]);  % Zoom-in

%hdlfilterserialinfo(hcas,'InputDataType',numerictype(1,1))%display valid serial partitions

So the filter matlab code is done and I was trying to convert it to VHDL with Filter Design HDL Coder ( unfortunatly I have no expirience with VHDL and no time at the moment to learn it - hope I'll fix it soon...)

I have a 1 bit Input in the first stage (CIC), so I tried to fix the input with inT = numerictype (1,1) for unsigned 1 bit input and generate the vhd files:

inT = numerictype(1,1);
generatehdl(hcas,'InputDataType', inT,...
'Name','filter','TargetLanguage','VHDL',...
'TargetDirectory',fullfile(workingdir,'hdlsrc'),'GenerateHDLTestbench','on','TestBenchName','FilterTB');


But Matlab gives me an error „HDL generation supports double and signed fixed point (binary point scaling) inputs.“

But I can’t screate a signed 1 Bit input, what should I do?

Thanks!
 

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