Taki_comp
Member level 1
I am trying to implement an image acquisition system that communicates between Matlab and PC, the system works as follows: first of all matlab reads a grayscale image of resolution of 512x512 where the colors are 8-bit coded, the image then is segmented into 512 segments, each of them represents one row of the image. On the FPGA side, I used Ip core generator to generate a block of simple dual port RAM of size 512 bytes, this BRAM is interfaced with two UART interfaces; receiving interface and transmitting interface, the receiving interface receives 512 bytes and stores them in BRAM, then the transmitting interface sends back those 512 bytes to the Matlab software, this process is supposed to be repeated 512 times to send the whole image. Finally, the image received from FPGA is displayed on Maltab.
here is the vhdl code for the fsm used to control the operation of the UART
The Matlab code used to transmit and receive the image is shown below
This is the picture of the Matlab command line after executing the Matlab program
As you can see the Matlab excutes the loop only 2 times, furthermore for the third iteration Matlab reads only 480 bytes so it remains busy until the timeout is elapsed, what are the possible reasons for this error ?
here is the vhdl code for the fsm used to control the operation of the UART
Code:
proc_next_state: process(clk, reset, state)
begin
if reset = '1' then
state <= idle;
elsif (rising_edge(clk)) then
case state is
when idle =>
count <= 0;
wea(0) <= rx_dv; -- set write enable equal to rx data valid signal
dina <= rx_byte; -- input of BRAM's port A.
ENB <= '0'; -- Enable signal for port B
tx_DV <= '0'; -- data valid signal for uart transmitting interface.
tx_byte <=(others => '0'); -- byte to be loaded to uart transmitting interface
if rx_dv = '1' then -- data valid signal for uart receiving interface
state <= writing; -- if rx_dv is asserted move to the writing state
else
state <= idle; -- keep idle
end if;
when writing =>
if addra = Addr_max then -- if the whole block is written move to the reading state
state <= reading;
else
state<= idle;
end if;
wea(0)<= '0';
dina <= rx_byte ;
ENB <= '0';
tx_DV <= '0';
addra <= addra + 1;
tx_byte <= (others => '0');
when reading =>
If count = 0 then
ENB <= '1';
tx_DV <= '0';
state <= reading;
elsif count = 1 then
ENB <= '0';
tx_DV <= '0';
state <= reading;
else
if addrb = addr_max then -- if the 16 bytes data are fully read move to state done
state <= done;
else
state <= waiting;
end if;
ENB <= '0';
tx_DV <= '1';
addrb <= addrb + 1;
end if;
tx_byte <= doutb;
wea <= (others => '0');
dina <= (others => '0');
count <= count + 1;
when waiting =>
count <= 0;
wea <= (others => '0');
dina <= (others => '0');
ENB <= '0';
tx_DV <= '0';
tx_byte <= (others => '0');
if tx_done = '1' then
state <= reading; -- read a new byte when tx_done is asserted high
else
state <= waiting; -- keep waiting
end if;
when others => -- remain in this state for one clock period then move to idle
wea(0) <= '0';
dina <= (others => '0');
ENB <= '0';
tx_DV <= '0';
tx_byte <= (others => '0');
Addra <= (others => '0');
Addrb <= (others => '0');
pass_sig <= pass_sig + 1;
state <= idle;
end case;
end if;
end process;
The Matlab code used to transmit and receive the image is shown below
Code:
ImgOrig = imread('Dome.gif'); % read the image into a matrix of dimension 512x512
ImgCopy = zeros(512,512);
s = serial ('COM3');
set(s,'baudrate', 115200);
set(s,'Databits', 8);
set(s,'stopbits',1);
set(s,'InputBufferSize', 512);
set(s,'OutputBufferSize', 512);
set(s,'Timeout',120);
dataWr = zeros(512,1);
dataRd = zeros(512,1);
i = 1;
fopen(s);
while(i<= 512)
tic;
for j = 1:1:512
dataWr(j)= ImgOrig(i,j);
end;
fwrite(s,dataWr,'uint8');
dataRd = fread(s,512,'uint8'); % data read from BRAM of FPGA
for j = 1:1:512
ImgCopy(i,j) = dataRd(j);
end;
i = i+1;
toc;
end;
fclose(s);
Imshow(ImgCopy);
This is the picture of the Matlab command line after executing the Matlab program
As you can see the Matlab excutes the loop only 2 times, furthermore for the third iteration Matlab reads only 480 bytes so it remains busy until the timeout is elapsed, what are the possible reasons for this error ?