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vector waveform quartus

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V

vead

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Hello
I wrote verilog code for AND gate and now I want generate vector waveform 
Code Verilog - [expand]
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module and_gate(a,b,y);
input a,b;
output y;
assign y=a&b;
endmodule

I compiled code there is no error. than I select new file->vector waveform. can you tell me how I have to do to generate vector waveform
 

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Never used these draw the waveform type of simulators. But I'm assuming you probably have to add the signals into the waveform window and draw the signals.

You would be better off learning how to write a testbench and running this in Modelsim AE. That at least gives you marketable skill, unlike learning that Quarus vector drawing tool.
 

Mostly agree with ads-ee. Vector waveform editor has been used with the old Quartus built-in simulator, available till V9 or so. Later Altera provided a converter in the University Program that drives Modelsim from the waveform file.

I still find the simulator appropriate for small simulation problems.

can you tell me how I have to do to generate vector waveform
Click to expand...
You'll start by adding signals, then select a signal and use the self-explanatory icons to define stimuli for the input signals.
 

FvM said:
You'll start by adding signals, then select a signal and use the self-explanatory icons to define stimuli for the input signals.
Click to expand...

Pretty much they way I thought you would have to enter them, All the waveform creation tools seem to work the same way. I've used Timing Designer and a couple of other similar tools in the past.

- - - Updated - - -

A testbench like this would check all valid input combinations (invalid ones like U, X, and Z are not checked).
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// code untested...
`timescale 1ns/1ps
module and_tb;
 
  reg   [1:0]   cnt = 0;
  wire          and_out;
 
  reg           clk;
  initial begin
    clk = 0;
    #5 clk = ~clk;
  end
 
  always @ (posedge clk) begin
    cnt <= cnt + 1;
  end
 
  and_gate  uut (
    .a  (cnt[0]),
    .b  (cnt[1]),
    .y  (and_out)
  );
 
endmodule


You can also brute force it, but I seldom use that technique as it's not very maintainable...
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// brute force approach
`timescale 1ns/1ps
module and_brute_force_tb;
 
  reg     a,b;
  wire    and_out;
 
  initial begin
    a = 0;
    b = 0;
    #10;
    a = 1;
    b = 0;
    #10;
    a = 0;
    b = 1;
    #10;
    a = 1;
    b = 1;
    #10;
  end
 
  and_gate  uut (
    .a  (cnt[0]),
    .b  (cnt[1]),
    .y  (and_out)
  );
 
endmodule
 

. Do you have quartus? Do you use? I just wanted to know behavior of signals. I want to make block schematic diagram, and time diagram. Is it possible with quartus? Suggest me, what I do
 

I've used Quartus in the past but haven't used it for about 3-4 years.

To generate a schematic of the circuit you can just have Quartus produce a RTL schematic view (or something like that) or a Technology view (not sure if that is what they call that either). To get a timing diagram try one of the testbenches and run a simulation with all the signals displayed in the waveform window.

Not sure what your objective is with doing all this...seems rather pointless to me. An AND gate is an extremely simple thing and the truth table should be enough to understand it.
 

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