Optical communication between two FPGA boards -- syncing clocks?

I am working on something where I will have optical communication between two boards. One board will generate specific pulse, another will receive it.

To simplify things, I will have same clock speed on both boards. However, how do I synchronize them to make the receiving FPGA pick up incoming signal?

You might try the type of computer communication back in the day when we spoke of 300 or 1200 baud. You set both units to the same baud rate. The receiving computer keeps time as each new byte (series of 8 or 9 bits) is received. Each bit is either a high or low. Suppose there are several zero's in a row. The signal remains low for an extra long time. The receiving computer must interpret this properly as a certain number of zero's. This means the receiving computer needs to be flexible about its timekeeping. It needs to adapt to the incoming signal.

Two clock residing on two different boards using two different clock source (i.e. oscillators) can not be synchronized as they are dependent on a fundamental frequency of something that is dependent on voltage/temperature/etc. So it's pretty much guaranteed that the two clocks will not be in phase or have exactly matching frequencies.

If you are sending a single clock wide pulse there will likely be intermittent capture problems as the two clocks drift.

So what exactly are you trying to accomplish with this optical communication link sending a pulse? Is it to keep track of some time position or something else entirely? Give us a clue so we can perhaps make a better suggestion than using a UART like protocol to detect bits (if you even wanted to transfer data and not a periodic signal signifying a relative positions in time).

UsernameIsValid said:

I am working on something where I will have optical communication between two boards. One board will generate specific pulse, another will receive it.

To simplify things, I will have same clock speed on both boards. However, how do I synchronize them to make the receiving FPGA pick up incoming signal?

Click to expand...

Serial communication is either Async or Sync. If sync then Rx must bit sync, word sync and frame sync like SDLC.

What data rate, protocol would U like to use?

Hi,

If you choose the right concept you could sync the receiver to the transmitter with a pll.

Like LVDS serializer/deserializer do.
Or the gigabit transmission.

*****
A simple example*
If you send a continous pulse signal with fixed frequency and fixed timing from rising edge to rising edge...
Then the receiver could use the rising edge to generate a clock with a pll that is synchrounous to your transmitter system clock.
The information (data to transmit) is in the duty cycle = time from rising edge to falling edge.

0% duty cycle and 100% duty cycle is not allowed.
Depending on frequency maybe 10% to 90% is usefull.
For higher data rate with just sending 0 and 1 you could use 25% / 75% or 33% / 67% for 0 / 1 and just read in the state of the line at 50%...

Klaus

In most synchronous serial data links, the receiver recovers the clock from the data stream and synchronizes a PLL to it, e.g. with USB, Ethernet, PCIe, SATA.

Under circumstances, it's wanted to synchronize the system clock of a slave system to the recovered master clock or to a time mark distributed periodically by the master.