ammar_kurd
Junior Member level 3
I am trying to write a synthesisable Verilog module for a JK with a reset, I have tried this
But I get this warning :
And if I add the reset signal to the sensitivity list like this:
I get this warnings:
It shows that reset is never used! how so? what is the proper way to write a synthesisable JK flip flop in verilog?
Code:
module JK_FF(
input J,
input K,
input reset,
input CLK,
output reg Q
);
always @(posedge CLK) begin
if (reset == 1'b0)
begin Q <= 1'b0; end
case({J,K})
2'b0_0 : Q <= Q;
2'b0_1 : Q <= 1'b1;
2'b1_0 : Q <= 1'b0;
2'b1_1 : Q <= ~Q;
endcase
end
endmodule
But I get this warning :
Code:
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
And if I add the reset signal to the sensitivity list like this:
Code:
always @(posedge CLK or negedge reset) begin
I get this warnings:
Code:
WARNING:HDLCompiler:91 - "/home/verilog_workspace/Ripple_counter/JK_FF.v" Line 15: Signal <J> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:91 - "/home/verilog_workspace/Ripple_counter/JK_FF.v" Line 16: Signal <Q> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:91 - "/home/verilog_workspace/Ripple_counter/JK_FF.v" Line 19: Signal <Q> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <Q>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
It shows that reset is never used! how so? what is the proper way to write a synthesisable JK flip flop in verilog?