Help me in FIR Verilog code

Aug 16, 2016

elec_eng92

Newbie level 1

hello

i am doing a verilog project that design a FIR filter.

i generate sin & cos waves with cordic algorithm and apply it to FIR fiter.

i am not sure about response.

this is the code of fir filter:

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
module FIR_filter(input signed [15:0]x, input clk, output reg signed [31:0]yn);
 
reg signed [15:0] xn[4:0];
wire signed [31:0]v;
 
wire signed [15:0] h0=16'h0325;
wire signed [15:0] h1=16'h1e00;
wire signed [15:0] h2=16'h3DB6;
wire signed [15:0] h3=16'h1e00;
wire signed [15:0] h4=16'h0325;
 
assign v=(h0*xn[0]+h1*xn[1]+h2*xn[2]+h3*xn[3]+h4*xn[4]);
 
always@ (posedge clk)
begin
 
xn[0]<=x;
xn[1]<=x[0];
xn[2]<=x[1];
xn[3]<=x[2];
xn[4]<=x[3];
 
yn <= v;
 
end
endmodule

Code Verilog - [expand]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26	module FIR_filter(input signed [15:0]x, input clk, output reg signed [31:0]yn); reg signed [15:0] xn[4:0]; wire signed [31:0]v; wire signed [15:0] h0=16'h0325; wire signed [15:0] h1=16'h1e00; wire signed [15:0] h2=16'h3DB6; wire signed [15:0] h3=16'h1e00; wire signed [15:0] h4=16'h0325; assign v=(h0xn[0]+h1xn[1]+h2xn[2]+h3xn[3]+h4*xn[4]); always@ (posedge clk) begin xn[0]<=x; xn[1]<=x[0]; xn[2]<=x[1]; xn[3]<=x[2]; xn[4]<=x[3]; yn <= v; end endmodule

Youtf is the out of filter and Xout & Yout is out of cordic module.

is the output correct? why?

can anyone help me? I am really cofused!

thanks

Last edited by a moderator: Aug 16, 2016

Welcome to EDAboard.com

Help me in FIR Verilog code

elec_eng92

Newbie level 1

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Connect with us

Online statistics

Forum statistics