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How to improve the settling time

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predator89

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I have designed class AB folded cascode OTA (Image attached ref. J Huijsing). I want to achive less than 20 ns settling time.

I found that i acheive better settling near to 60 deg phase margin and above and below it the settling time reduces. So at corner simulation I am not able to achevie the required settling time.

Also there is trade off between phase margin and UGF and slew rate. As i try to increase the phase margin both UGF and SR decrease.
Can anyone suggest solution to acehive better settling (15 ns)
ClassAB_FoldedCascode.png
 

Settling time is about both the op amp design and its load.
Probably begin with, is settling (with spec load) dominated
by the load C and output stage drive strength (R) or is it
dominated by overshoot and damping from the other side
(or, is it so marginally stable that ringing sets the mark)?

You have to have the drive strength (at not much input
overdrive, or this becomes another problem) such that
bang-bang transition time is maybe 5nS, and then the
compensation has to control that.

A hard Miller compensation with no zeroes is going to
cost you in slew rate and unity gain frequency.
 
Try to use cascode compensation or/and increase ft of your load transistors (with cost of gain - probably You will have to decrease length of current sources or increase their overdrive).
 
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