ChanKim
Newbie level 4
Hi,
It's been years since I worked on Verilog design last time.
To do a simple test, I tried running Verilog simulation and I get this warning during simulation. and I can't see the signals in simvision window.
The line I get this error is marked below (by '<=== here')
in another post I searched, someone suggested using ncverilog --access rwc but my command is ncvlog. (not ncverilog) and it doesn't understand the option.
ncvlog: *F,BADOPT: unknown or ambiguous options (--access) (for command ncvlog --access rwc tb_conv.v)
my cds.lib file :
and my hdl.var :
I'm using INCISIV12.2. THanks!
It's been years since I worked on Verilog design last time.
To do a simple test, I tried running Verilog simulation and I get this warning during simulation. and I can't see the signals in simvision window.
WARNING: SYSTF DBPRVIS
For the requested database probe some object did not have read access
The line I get this error is marked below (by '<=== here')
Code Verilog - [expand] 1 2 3 4 5 6 initial begin $recordsetup("design = tb_conv", "directory = rtl_wave.shm", "run = 1"); $recordvars("depth = 0", tb_conv); <=== here $recordon; $display("#sim started"); end
in another post I searched, someone suggested using ncverilog --access rwc but my command is ncvlog. (not ncverilog) and it doesn't understand the option.
ncvlog: *F,BADOPT: unknown or ambiguous options (--access) (for command ncvlog --access rwc tb_conv.v)
my cds.lib file :
Code:
DEFINE work ./work
INCLUDE $NC_HOME/tools/inca/files/cds.lib
Code:
DEFINE WORK work
Last edited by a moderator: