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How to represent negative numbers without using two's compliment method in Verilog?

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how to represent negative numbers without using two's compliment method in verilog?
what will be the putput for this..-4'd8 / 4'd2..will i get -6 in modelsim simulator..how to check or verify the answer.
 

verilog

You can put an extra bit that represents the sign bit (1 for negative numbers and 0 for positive).
Use the signed represantation of numbers in modelsim to check the result
 

Re: verilog

There are three mathos to represent the negative no.
1). sign-magnitude representation :- just add one bit to the normal binary no. just to show that its negative.
2). 1's compliment :- invert all the digits
3). 2's compliment :- add 1 to 1's compliment version.
in implementation each have pros and cons

modelsim will accept if you tell it the representation for -ve no.
just read some good book on digital design and proceed
 

verilog

how to represent negative numbers without using two's compliment method in verilog?
Click to expand...
Obscure sneaky solution: use a real number! The IEEE 754 floating point format contains a sign bit, a positive exponent field (with implied bias), and a positive fraction field. It has no two's compliment parts.
 

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