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Synchronous multiplier using VHDL

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rrk

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I have to design a synchronous 3*3 bit multiplier in VHDL without using the operator *.It has to be a FSM . I tried several times but the outputs are not correct. Can someone help me with any resources online or maybe a some guideline steps plz!
 

why do u use an FSM ? what kind of multiplier do u want to do signed or unsigned?
what kind of FPGA you r using?
 

Hi rrk,
if u r not supposed to use a * operator, then use loops in ur coding to perform repetitive addition.
 

hi rrk,
why cant u try any multiplier algorthim such as booth, bough-wooley ,
 

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