Design of sample and hold for 4-bit flash ADC :: HELP

Hello,
I am working on a project to design a 4-bit Flash ADC for a digital transceiver.The flash ADC should meet the following specifications:
Input frequency: 100MHz-500MHz
Sampling Rate: 2GS/s
VDD= 1.1V
signal voltage range = 0.5V peak-peak

I am using cadence with umc 65 technology.

I am having a small issue when designing the sample and hold. I have used the open-loop architecture for fast switching and lower power. It is a mix of complementary input switch(NMOS AND PMOS) and a bottom plate switch as well.

I am getting some pedestal errors and sampling errors(error between original signal and sampled signal at the instant of sampling). I would like to know what is the acceptable range for the pedestal and sampling errors. Also, is there a way to reduce these errors ? The max pedestal error i am getting is 18mV. Max sampling error is 15mV

Hi,

I never used a true flash ADC. I always thought they don´t need a S/H circuit. But I may be wrong.

Klaus

If you consider any other ADC, what would be the acceptable % of pedestal and sampling errors when compared to 1 LSB of ADC ?

I'm thinking at 2GSPS this is a RF application and you
don't care about DC accuracy. If the sampling error is
-constant- across the input range then maybe it gets
processed out, no foul.

Also at 2GSPS I'd think this is a 50-ohm system and
you'd rather not have an amplifier to design, maybe
this is just a dumb switch and the Cin of the ADC.
If 50*Cin is higher than 1/(2GHz).

A complement-driven dummy FET can do some
sampling-kick compensation at the switch.