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Using Asynchronous reset as logic

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Dar89

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Hello,

I have to solve a problem end the most effective way I have found is to put some logic on the asynchronous reset pin of a flip-flop. I can do this by putting and AND between the global_reset (which is and asynchronous reset, but synchronized before driving registers) and a control signal, as reported in the following. Do you see any reliability issue in this code?

Code Verilog - [expand]
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module(clk, sync_rst, T, In, Out)
 
input clk, sync_rst, T, In;
output Out;
 
reg T_reg;
wire int_rst;
 
assign int_rst = !(sync_rst & T_reg);
 
always @(posedge clk) 
   T_reg <= T;
end
 
 
always @(posedge clk, negedge int_rst) 
begin
  if(int_rst )
         Out <= 1'b0;
  else
       if(T)  //clock gating
           Out <= In; 
end 
 
endmodule
 
Last edited by a moderator:

Hmm...

Typos in this code, missing module name, missing begin, also mixed case (carpel tunnel inducing shift key), along with antiquated Verilog port declarations. All bad coding habits IMO.

I'm wondering why you have "sync_rst & T_reg"? The only way the T_reg will work is if the reset is active (assuming sync_rst is active high given the ! in front). Also not sure why you would add an inverter to the rest path to make your reset negedge is that due to there only being active low reset Flip-Flops in the library?

You really want | instead of & if you want T_reg to reset the Out FF.

This circuit makes me cringe though, but maybe it's standard practice in ASIC design nowdays?

If all you wanted to do was clear Out 1 clock cycle after T goes high, i.e. only have Out update once at the leading edge of T and get cleared on the next clock cycle.
Code Verilog - [expand]
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assign int_rst = !sync_rst;
always @(posedge clk or negedge int_rst)
  if (!int_rst) Out <= 1'b0;
  else if (T && !T_reg) Out <= In;
  else if (T_reg) Out <= 1'b0;
 

ads-ee said:
Hmm...

Typos in this code, missing module name, missing begin, also mixed case (carpel tunnel inducing shift key), along with antiquated Verilog port declarations. All bad coding habits IMO.

I'm wondering why you have "sync_rst & T_reg"? The only way the T_reg will work is if the reset is active (assuming sync_rst is active high given the ! in front). Also not sure why you would add an inverter to the rest path to make your reset negedge is that due to there only being active low reset Flip-Flops in the library?

You really want | instead of & if you want T_reg to reset the Out FF.

This circuit makes me cringe though, but maybe it's standard practice in ASIC design nowdays?

If all you wanted to do was clear Out 1 clock cycle after T goes high, i.e. only have Out update once at the leading edge of T and get cleared on the next clock cycle.
Code Verilog - [expand]
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assign int_rst = !sync_rst;
always @(posedge clk or negedge int_rst)
  if (!int_rst) Out <= 1'b0;
  else if (T && !T_reg) Out <= In;
  else if (T_reg) Out <= 1'b0;
Click to expand...

Excuse me for the typos, I wrote the code so fast. I'll try to follow your advices regarding code style, but what do you mean with "antiquated Verilog port declarations"?

However, I want, essentially, that my flip-flop must:

- be resetted on the negedge of sync_rst or of t_reg
- must be updated when t is high (it is an enable and I want perform clock gating based on this)
- when t goes to zero (enable disabled) the flip-flop must be clock gated, but for me it is essential that it goes in clock gating memorizing a zero (this is the reason why I'm putting on the asynchronous logic path the signal t_reg).

I'm using an active low reset, because the circuit that I'm designing is resetted on the active low reset.

Code: 
[syntax=verilog]module  test_reg(clk, sync_rst, t, in, out);
 
input clk, sync_rst, t, in;
output out;
 
reg t_reg, out;
wire int_rst;
 
assign int_rst = (sync_rst & t_reg);
 
always @(posedge clk) 
begin
   t_reg <= t;
end
 
 
always @(posedge clk, negedge int_rst) 
begin
  if( !int_rst )
         out <= 1'b0;
  else
       if(t)  //clock gating
           out <= in; 
end 
 
endmodule
[/syntax]
 

Antiquated as in Verilog 2001 syntax for port declarations is supported by every single tool I've used/seen and doesn't require that you to repeat the names of the ports.

What you are doing isn't technically clock gating at all, synthesis tools that can do that use the enable and insert a clock gating cell into the clock that drives the FF. You aren't doing any of that you're just resetting the FF.
 

this is confusing. synthesis tools can infer both enable logic as well as clock gating logic.

it's been decades since the last time I saw someone write clock gating logic manually.
 

ThisIsNotSam said:
this is confusing. synthesis tools can infer both enable logic as well as clock gating logic.

it's been decades since the last time I saw someone write clock gating logic manually.
Click to expand...

Clock gating logic can be inferred by synthesis tool, I know, but I needed to have a register that was clock-gated, storing a zero. The approach that I was trying to use was stupid, but I solved in a different way, and the tool is correctly managing the clock gating.

Thank you.
 

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