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[SOLVED] How to add the body connection for a UMC 180 triple well nmos?

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vineel13

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I've designed a circuit which uses body biasing for NMOS. For this, I've used the UMC-180nm's BPW N_18 transistor from their library for making the schematic. Now to make this layout I generated it from the schematic and got a predefined layout for this triple well transistor, but I don't know where to add the body connection in this generated layout. Any kind of help regarding this is appreciated.

- - - Updated - - -

bpw.png

That is the layout generated for the n_BPW_18_mm transistor.
Where and how can the body be added in this?
 

Hi,

just make a connection between red area (diffusion) and metal. In other words, put a contact on diffusion (red) and connect it with GND by metal line. Because Body (Bulk) is a silicon wafer.

If you have any further questions, please do not hesitate to ask here :)
 

Because I have to do some body biasing I need a body contact through which I can apply the voltage?
But I'm not sure where to add this contact. Logically it has to added in because the twell(green) and nplus ( brown rectangle) but the spacing between them is very less?
 

... twell(green) and nplus ( brown rectangle) but the spacing between them is very less?

Are you sure that twell (the nwell) is inside the green rectangle and the p region (not nplus) for the NMOS is inside the brown rectangle?

May be the twell (the nwell) is inside the white rectangle and the p implant region is inside the green rectangle? The green rectangle then would fully comprise the p- implant (the body) region for the NMOS. The brown rectangle contains the n- implant (the "diffusion") for the NMOS itself, and the green rectangle below the red n+ implant is the n+ contact to the white metal1 rectangle inside it? Check your LSWindow for the layers' colors!

If so, I'd think at least in the corners of the green rectangle there should be enough space for a p+ contact with metal1 to connect to GND. For an n+ contact within the brown rectangle is really not much space. Probably in the (other) corners, also?

Inside the (big) white nwell rectangle you need an n+ contact (better: contacts ring) with metal1 to connect to VDD.
 

I cross checked the layers information in this is what I got:
Outer white rectangle -> Nwel
Green rectangle -> twel
Inner yellow rectangle -> nplus
red area -> diff
violet -> poly
green squares -> con
 

Ok, then it's as I showed you above, apart from three different color and layer designations:

Your twel is my p- implant
your Inner yellow rectangle -> nplus is my brown rectangle p+ implant
(I designated it erroneously as n- implant, sorry! But your color designation was previously also brown)
your red area -> diff is my red n+ implant

... otherwise like above.
 

Now that the information about the layers has ben established, there isn't enough space for me to add (without DRC errors) an M1-Pdiff contact for the bulk within the green rectangle.

Is there anything I can do?
 

Try drawing some twel that extends out enough for you to drop in a M1-Pdiff contact. I wouldn't be too concerned with DRCs relating to nwell/twel etc. These would be healed at a higher level.
 

yeah that is what I did but there is still one DRC error but no LVS errors!
I made a huge Nwell rectangle and then added the Twell rectangle inside it. Now I used the premade layout of the NMOS N_18 and placed it in between the T well. I made the T well big enough so that there is space for me to add an M1-Pdiff contact and viola it worked with no LVS errors!
But there is this one DRC error "Minimum P+ implant overlap P+ diffusion (inside N-well) is 0.22um" . Can this error be skipped? or is it necessary to fix it before I go on?
 

... there is this one DRC error "Minimum P+ implant overlap P+ diffusion (inside N-well) is 0.22um" . Can this error be skipped? or is it necessary to fix it before I go on?

It's probably easy to fix: Just enlarge the P+ implant overlap over P(+) diffusion ≥ 0.22µm.

Diffusion isn't really P+, but P- . P+ implant must be either inside P diffusion, or must have a minimum overlap over it.
 
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