Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Why we choose phase margin of 45 or 60 degrees?

Status
Not open for further replies.
K

Karthikeya

Advanced Member level 4
Joined
Jan 9, 2005
Messages
103
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Activity points
987
why is it tht in most analog circuits we choose a phase margin of 45° or 60° for designing?

thnkx
 

Re: Phase margin

It is tradeof between stability and gain. To avoid oscilations in feedback amplifier, phase must be less that 180 at unity gain frequency. You can make frequency compensation with less phase margin, to obtain bigger gain at lower frequency, but you risk to make oscilator, not amplifier.
 

Re: Phase margin

It can be proved as a general case that given a phase margin of 60° the amplifier's step response will not have any peaking, thus very less possibility for it to become stable. Thus 60 degrees is normally chosen to be the phase margin.
45° degrees is taken as a tradeoff, to have faster risetime and less settling time.
 

    K

    Karthikeya

    Points: 2
    Helpful Answer Positive Rating
Re: Phase margin

In some situations when you need to achieve higher bandwidtha, smalll peaking of 4.3% can be tolerated. This response has phase margin 64, and is called Butterworth response. For higher phase margin, peaking much more disturbs signal.
 

Re: Phase margin

Check this one, a summary about optimal phase margin.
 
Re: Phase margin

i dont believe on this 60 degree PM concept..
for critical dampling, PM shd be close to 70 degree at Wcl...
and u can achieve that by setting ur nondom pole freq:
Pnon=3*Wcl (feedback factor=1)
Pnon=2.5*Wcl (feedback factor=3)
Pnon=2*Wcl (feedback factor>5)
 

Re: Phase margin

thnkz everybody
one more question...........how do i define phase margin if mag plot crosses 0db more than once??
which systems usually hv such response??? can ne1 give an example
 

Phase margin

Can you post your ac simulation graph of circuit?
Let me konw why your circuit has odb more than
once!
 

Re: Phase margin

paladinzlp said:
Can you post your ac simulation graph of circuit?
Let me konw why your circuit has odb more than
once!
Click to expand...
It happens when ur system hav complex nondominant pole pair..
u hav to check the PM at the last Gain Crossover..(or wherever the PM is lowest)

Plz press the "helped me" button if i really helped u..

c ya
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top