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Calibre LVS_ IC6 TSMC0.18 PCell

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Tahirmis_ic

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Hi everyone,

I am using TSMC18 with Cadence IC6, and when I run Assura LVS, Schematic and Layout match, But when I run Calibre LVS, it finishes with "Nothing in layout".

To know the origin of this problem : I flatten my PCell, and when I show the properties of some layers (with Q) I have in the title of the window of properties " Edit Rectangle Pin Properties" and the layer is in "Diff" "Drawing": Calibre is sensible to layers in this configuration. So when I just draw layers in "Rectangle properties" on layers in "Rectangle Pin Properties", Calibre LVS works and there is the famous match." (please see

flatten.png)

So does someone know how can I solve this problem please?

By hoping to have been clear, thank you,

Mohammed
 

This is perhaps too basic, but... is IC6 set to export the layout to Calibre? Is the pcell listed in an LVS Box statement as something to be ignored?
 

Maybe Caliber netlisting is not set up with the right switch /
stop views? Or, maybe it's the scheme of assigning connectivity
which I am seeing sometimes is the old property-on-polygon,
and other times a label on layer (for example) m1port/dwg. A
layout entity created under one verification suite may be
constructed differently in the details, than one meant to be
verified (and reused, and reverified) under another tool-set.

Is your Caliber deck coming from TSMC themselves? Or a
third party stab at an Assura-equivalent checking? You
are almost always best off at the source, if they'll talk
to you (and a help ticket will tell you that, for nothing).
 

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