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IR drop questions and clarifications

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meeyaw

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Hi,

I have question that currently tricks me. Here is diagram for the reference for my questions
IR_drop.png

gpwr is a power gated supply when PWRPMOS is enabled.

1.In my current SPICE run, the bounce on the gnd is higher that drop in the pwr rail. Is that possible?

2. Based on the diagram, i expect that worst IR drop (ground bounce) be found on rightmost buffer (which is 1x), but it appears that the last 10x had the worst ground bounce. Is the size of the buffer plays a role on IR analysis?

Note: buffers are 100MHz drivers

Thanks for any replies. Just need to hear someone to clarify my confusion.

Thanks,
meeyaw
 

Since many parasitics are returned to ground (substrate) it is
not unreasonable that the ground bounces hardest. The stray
C from gpwr to gnd adds to gnd bounce.

Since you show no series R anywhere, it seems unreasonable
that the various buffers would have different ground bounce
on a schematic-based simulation. To debug, look at your
netlist ground connectivity vs your concept schematic - the
buffers may be differently arranged between the two, with
the interconnect resistors making each point unique (not
the case, as drawn).
 
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    meeyaw

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Hi,

Thanks for the reply. By the way, can you expound the first paragraph more? Is that stray capacitance is equivalent to capacitance of the power rails when you use parasitic extraction tools?

Thanks,
meeyaw
 

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