Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

illegal bus reference cadence

Status
Not open for further replies.

preethi19

Full Member level 5
Joined
Jun 30, 2014
Messages
273
Helped
0
Reputation
0
Reaction score
1
Trophy points
16
Activity points
3,474
Hi i have a idc source (i1) wer the +ve terminal is connected to drain of a transistor wer another pin (i2) is already given. And the
-ve pin of the idc source (-i1) to second transistor drain and same to this second transistor drain another pin (i2) is given. I need to do the layout too. But i am getting an error

ERROR:Illegal bus reference - Can't tap "<i1>" from net "".
Can anyone pls let me know how to correct this error. And i am sure if i try connecting two different pins on a same metal in layout it will give the error "label pin on net with different name". So can anyone help me both in schematic and layout of how to avoid the errors in both.. Thanks a lot!!! :)
 

A node name between angle brackets - like your <i1> - is always expected as a bus net name. As the tool can't find the bus definition, it reports this error.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top