pass Tx of LDO for VCO application

Hi

Designing LDO for vco app. At LDO output cap is 2pF. NMOS is used as pass Tx. Load current steps from 0 to 30mA. Pass Tx coming to SAT region after load current reaches 15mA, before it is remaining in Subthresold region. Is it compulsory for NMOS Pass Tx to get saturation at 1mA itself?

Thank u in Advance
satya

I think an LDO pass-Tx should always operate in saturation region to allow for good regulation. If - at high output current - its operation point moves below its saturation voltage into the triode region, the LDO gain gets worse, so the output error increases.

PLL should not have an especially variable load, why
such a wide range of operating current, or is this only
a startup phase and normal operation can be tighter?
Distinguish between the overall line-/load-space, and
the region where you are actually on the hook for
accuracy, ripple rejection and so on.

Hai,

Thanks for your reply. Its going to subthresold region (no triode region) at load currents(0--15mA),and above 15mA it comes into saturation region. my topology is first stage diffamp having diode connected looad followed by common soure amp and then followed with NMOS pass Tx in source follower config. Dominant pole at the output of error amplifier. Because of load variations(0 to 30mA) there is impedance variation at the LDO output, which effects pole location. so at no load having phase margin of 55 deg and at full load condition having PM of 78 deg. is it ok? And in load transient simulation the regulated voltage is having spike of +100mV and -100mV. Are these results ok? please give reply.
Thanks
satya

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Hi ,

Thanks for your reply. Its an LC osc. In VCO because of switching we will have variations of current. can u elaborate on your comment

"Distinguish between the overall line-/load-space, and the region where you are actually on the hook for accuracy"

Click to expand...

Thanks
satya

analogdesigncdac said:

Its going to subthresold region (no triode region) at load currents(0--15mA), and above 15mA it comes into saturation region.

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Subthreshold shouldn't be designated as a region (it doesn't mean a region on the Ids vs. Vds characteristic): It is an operation mode, see this explanation.

But you're right: for low currents, a big MOSFET operates in subthreshold mode.

Its operation point will be shifted towards the triode (or linear) region for the highest output currents, i.e. when the input-output voltage difference falls below Vds,sat at these high currents. This determines the max. output current.

analogdesigncdac said:

... at no load having phase margin of 55 deg and at full load condition having PM of 78 deg. is it ok?

Click to expand...

Very good! But always specify the load capacitance for such results.

analogdesigncdac said:

... in load transient simulation the regulated voltage is having spike of +100mV and -100mV. Are these results ok?

Click to expand...

This depends totally on the application. Some can tolerate it, others not. Spike height depends (not only) on your LDO's load capacitance - but so does your PM.