sh-eda
Member level 1
Hi,
I'm relatively new to VHDL and I wonder if someone could have a look through this bit of vhdl code. The FPGA is a A42MX09, the IDE is libero.
I have simulated the code, before and after synthesis and it appears fine. Synthesis does not show any errors.
Basically it's a serial data stream, that sends 28bits of data. I was adding a simple 8bit sum of bytes checksum calculation as the last byte.
I have programmed it into an FPGA but it did not work. From checking the oscilloscope the only data that is being sent is the '0101' that I've added to make a byte up.
It appears to be intermittent, sometimes it does work, so I'm guess there's a race condition or timing issue happening.
I'm wondering if it that I am assigning 'tx_reg' in two places, but I'm not sure.
I've attached the full code.
Thanks
I'm relatively new to VHDL and I wonder if someone could have a look through this bit of vhdl code. The FPGA is a A42MX09, the IDE is libero.
I have simulated the code, before and after synthesis and it appears fine. Synthesis does not show any errors.
Basically it's a serial data stream, that sends 28bits of data. I was adding a simple 8bit sum of bytes checksum calculation as the last byte.
I have programmed it into an FPGA but it did not work. From checking the oscilloscope the only data that is being sent is the '0101' that I've added to make a byte up.
It appears to be intermittent, sometimes it does work, so I'm guess there's a race condition or timing issue happening.
I'm wondering if it that I am assigning 'tx_reg' in two places, but I'm not sure.
I've attached the full code.
Thanks
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 begin if reset = '1'then tx_out <= '0'; counter := 0; tx_reg := (others => '0'); elsif clk'event and clk= '1' then counter := counter + 1; if counter = 1 then tx_synch <= '1'; tx_reg := tx_data_bus ; ---- <<<<<<<<<<< -- Checksum calcs----------------------------------- -- Calculation is the sum of bytes. -- Added "0101" onto the end of last 4 bits to make a byte. -- Checksum is the three bytes added together. -- This is now the last 8bits of data sent high_byte (3 downto 0) := tx_reg(19 downto 16) ; high_byte (7 downto 4) := Extradata ; checksum:= std_logic_vector(unsigned(high_byte (7 downto 0))+ unsigned(tx_reg(15 downto 8)) + unsigned(tx_reg(7 downto 0)) ) ; tx_reg(27 downto 20) := checksum ; ---- <<<<<<<<<<< Is this the problem? ---------------------------------------------------- tx_out <= '1' ; end if; if counter >= 2 then if counter <= tx_length-1 then tx_out <= '0'; tx_synch <= '0'; tx_out <= tx_reg (counter-2) ; end if; end if; if counter = tx_length then counter := 0; tx_out <= '0'; end if; end if; end process;
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