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Common Emitter non symmetrical gain

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thiagofinottimoraes

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Hello,

I have simulated on LTspice a very simple CE amplifier as attached - picture and .asc simulation.

No AC capacitor at the emitter, plain and simple CE emitter bias unbypassed, in this case gain is Av = -Rc / RE = 4.07.

It turns out that, as input is a perfect 1V sine, at Vout, negative swing reaches -3.82V, and positive swing goes to +4.11V. That is not so small to be disregarded.

Any ideas why negative swing doesn't reach its full value??

**broken link removed**
**broken link removed**
 

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  • Simul EC.zip
    762 bytes · Views: 81

The circuit shows expectable non-linearity caused by the exponential Ic=f(Vbe) transistor characteristic. It's only small due to the strong feedback, but still visible. The calculated gain is only valid for small signal.

You may want to calculate harmonics and THD using SPICE fourier analysis and decide if the amplifier's signal quality is sufficient for your application.
 
Look at Vc and Ve to see if the swing at the collector is approaching saturation of the transistor.

The method you used for DC bias is very sensitive to the gain of the transistor.
You should reduce the value of R1 and add a resistor from the base of Q1 to ground to provide a voltage divider and establish a reliable bias point that is relatively insensitive to transistor gain.
You want the collector bias point to be about half way between the supply voltage and saturation of the transistor.
For the collector and emitter resistor values you have, the saturation voltage is about 5V at at the collector.
 

@FvM: Exactly, right on spot! Thank you. :smile:

- - - Updated - - -

@crutschow, thank you for your input, you are right. This circuit will be used for didactic purposes only, so this configuration is to be explored, including its drawbacks.

But what I believe really explains its non linearity is, as FvM stated, Ic=f(Vbe). Any other reason in mind?

Thank you.
 

The biasing error is not causing the non-linearity. A transistor is basically non-linear. I changed its bias a little so that it is in the center of being saturated or cutoff but the Sim works with a single biasing resistor only with a transistor that has "typical" hFE. I also bypassed the emitter resistor so that there is no negative feedback and increased the output level but it is not clipping.
 

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  • transistor distortion.png
    transistor distortion.png
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The post #5 circuit produces of course huge distortions. The original circuit has about 0.05 % THD, there's only a very small amount of non-linearity due to the large internal feedback. It 's well biased around 11 V.

It turns out that the level asymmetry seen in post #1 is 99 % DC shift and only 1 % (about 3 mV) non-linearity. This happens because the bias point shifts slightly when the AC voltage is applied.
 

When the voltage gain of a transistor is 1 then its distortion is very low and it acts like a piece of wire that can replace it (except the transistor is an inverter).
 

thiagofinottimoraes said:
....................
@crutschow, thank you for your input, you are right. This circuit will be used for didactic purposes only, so this configuration is to be explored, including its drawbacks.

But what I believe really explains its non linearity is, as FvM stated, Ic=f(Vbe). Any other reason in mind?
Click to expand...
As FvM noted, you are not observing a non-linearity, it's a DC shift due to the long one-second start-up time-constant of the output C2 and RL. If you increase the simulation time to 10.01s and start taking data at 10s (10 time-constants) the plus and minus amplitude magnitudes become essentially the same.

Always be aware of start-up transients when doing a simulation.
In real circuit operation these transients are normally gone by the time you view the signal, but a simulation will show them unless you run the simulation long enough so that they have died out.
 
Last edited:
crutschow said:
As FvM noted, you are not observing a non-linearity, it's a DC shift due to the long one-second start-up time-constant of the output C2 and RL. If you increase the simulation time to 10.01s and start taking data at 10s (10 time-constants) the plus and minus amplitude magnitudes become essentially the same.

Always be aware of start-up transients when doing a simulation.
In real circuit operation these transients are normally gone by the time you view the signal, but a simulation will show them unless you run the simulation long enough so that they have died out.
Click to expand...

Right, just did it. Silly me I missed this. Absolutely right. Thank you everyone!
 

thiagofinottimoraes said:
Hello,

I have simulated on LTspice a very simple CE amplifier as attached - picture and .asc simulation.

No AC capacitor at the emitter, plain and simple CE emitter bias unbypassed, in this case gain is Av = -Rc / RE = 4.07.

It turns out that, as input is a perfect 1V sine, at Vout, negative swing reaches -3.82V, and positive swing goes to +4.11V. That is not so small to be disregarded.

Any ideas why negative swing doesn't reach its full value??
Click to expand...

You would be wiser to examine the DC output and avoid Vce<2V where saturation begins. By shift the Q operating point higher, with negative feedback or less bias current, you can get more symmetrical swing up to Vcc-2V.

That's all. WHen AC coupling ensure the load R is always greater than the Collector R to avoid starving Ic.
 
With a slightly better biasing scheme and larger coupling capacitors, you can get close to the required output swing with low THD.

The original circuit indicates a THD of 0.126%
 

Attachments

  • CE_amp.png
    CE_amp.png
    42.3 KB · Views: 99
Last edited:
Its distortion is low because it has a voltage gain of only 4 and its output level is only 1/3rd of its power supply voltage. The generator has zero impedance. If it is fed from a circuit having some impedance then there will be attenuation and less voltage gain (and less distortion) caused by the negative feedback from the collector to base biasing resistor.
 
  • Another method below/ using collector choke impedance with negative feedback.
  • Distortion is reduced only slightly due to high forward gain, and less feedback gain. Lower output impedance but also lowering input Z.

8069147100_1449368594.jpg
 
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