Questions on conversion between vcd to vec

Hi guys,

I'm trying to convert a .vcd file into a .vec file for simulation use by using command as below:

vcd2vec -nvcd vec0.vcd -nsig pjn225DigTop_2.sig -start 0 -stop 200000000 -nvec vec0_output_by_vcd2vec.vec

But the software always shows error messages as below:

WARNING: No matching signal found in VCD for "#in xdig.i_pd" specified in the signal info file
WARNING: No matching signal found in VCD for "#in xdig.i_sclk" specified in the signal info file
WARNING: No matching signal found in VCD for "#in xdig.i_sdi" specified in the signal info file
WARNING: No matching signal found in VCD for "#in xdig.i_xclk" specified in the signal info file
WARNING: No matching signal found in VCD for "#out xdig.TS_adc_EnL" specified in the signal info file
WARNING: No matching signal found in VCD for "#out xdig.TS_adc_fast" specified in the signal info file
WARNING: No matching signal found in VCD for "#out xdig.TS_adc_init" specified in the signal info file

The .sig is as shown below:

#in xdig.i_pd
#in xdig.i_sclk
#in xdig.i_sdi
#in xdig.i_xclk
#out xdig.TS_adc_EnL
#out xdig.TS_adc_fast[2:0]
#out xdig.TS_adc_init
#vih 3.6
#vil 0.0
#slope 10p

The according module in .vcd file is as below:

$scope module xdig $end
$var wire 1 $ i_pd $end
$var wire 1 ! i_sclk $end
$var wire 1 " i_sdi $end
$var wire 1 + i_xclk $end
$var wire 1 v TS_adc_EnL $end
$var wire 3 u TS_adc_fast [2:0] $end
$var wire 1 w TS_adc_init $end

I never saw a correct .sig file before, so I can just write the .sig file according to the guides searched on the Internet.

May you please let me know what's the correct format of .sig file in this case or where am I making mistakes in the file?

I'm grateful to all your kindly help. Thank you all