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LVS termbad.out error in cadence

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YasaswiKamireddy

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Hello all,

I have an issue with LVS. I am trying to implement a 4 bit 1's compliment circuit. So this has just 4 inverters in the schematics and I have used the same in the layout(four instances of inverter layout).With pins added properly I cannot get LVS netlist match.in the si.out file I see that the termbad.out there are some issues.The following link is a snapshot of the problem.Can anyone help me out with this.Thank you.

https://obrazki.elektroda.pl/9926583600_1448306850.png
 

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