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[SOLVED] Problem with Parameters in Verilog

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VuTang

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Hi all,
I'm designing a module in Verilog and need to use some parameters. For example, I have two parameters: 'a' and 'b' and the value of 'b' depend on 'a'. I use the folow code but It had not run yet.
Code: 
localparam a = 9, b = 10;
initial 
 if (a = 1) b = 2;
 else if (a =2) b = 3;

Which verilog statement is suitable for this case?

Thank you very much
 

"if (a=1)" is a valid statement and will set a to 1. It is true, so b will be 2.
 

Oh, I'm sorry, this is my mistake when typing. In my module (design with Vivado-Xilinx):
Code: 
parameter a = 9;
localparam b = 10;
initial 
     if (a == 1) b = 2,
     else (a == 2) b = 5;
and when I synthesis that module, I got a message: "[Synth 8-1727] cannot assign to non-variable b"
 

B is a localparam, and you already assigned it the value of 10.
 

TrickyDicky said:
B is a localparam, and you already assigned it the value of 10.
Click to expand...

I've already assigned 10 for b, but when parameter 'a' is changed I want to update b's value. How can I do it?
 

I've already assigned 10 for b, but when parameter 'a' is changed I want to update b's value. How can I do it?
Click to expand...
You can't parameters are constants, they are set at compile time.

But you can do something like this.
Code Verilog - [expand]
1
2
3

localparam b = (a == 1) ? b = 2
                        : (a == 2) ? b = 3
                                   : b = x;
 

Thanks for your answer, ads-see!
I follow your code and it works ok.
 

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