Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesizing a mux using case and if elsif statements results the same!!! How?

Status
Not open for further replies.
B

biju4u90

Full Member level 3
Joined
Dec 10, 2014
Messages
172
Helped
3
Reputation
6
Reaction score
3
Trophy points
18
Activity points
1,437
Here are my process statements for a 4:1 mux using 'if-elsif' and 'case' statements in VHDL.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12

process (A,B,C,D,sel)
   begin
      if (sel = "00") then
         Y     <= A;
      elsif (sel = "01") then
         Y     <= B;
      elsif (sel = "10") then
         Y     <= C;
      else
         Y     <= D;
      end if;
   end process;

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9

process (A,B,C,D,sel)
   begin
      case (sel) is
         when  "00"     => Y <= A;
         when  "01"     => Y <= B;
         when  "10"     => Y <= C;
         when  others   => Y <= D;
      end case;
   end process;

When I synthesized them in Spartan 3E, I got the same synthesized reports!! The technology schematic also looked the same!! How this is possible??

Code: 
=========================================================================
Final Results
RTL Top Level Output File Name     : mux_case.ngr
Top Level Output File Name         : mux_case
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 7

Cell Usage :
# BELS                             : 3
#      LUT3                        : 2
#      MUXF5                       : 1
# IO Buffers                       : 7
#      IBUF                        : 6
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s100evq100-5 

 Number of Slices:                        1  out of    960     0%  
 Number of 4 input LUTs:                  2  out of   1920     0%  
 Number of IOs:                           7
 Number of bonded IOBs:                   7  out of     66    10%
 
Last edited by a moderator:

They are the same because both describe the exact same hardware.

Both of them use sel in a mutually exclusive manner therefore the synthesis results are identical.
 

I have read that the tool will synthesize if-elsif and case statements in different style. It was also recommended to use case statements rather than using if-elsif. Is it correct then?
 

If all the selections are mutually exclusive and all possible selections are defined then it doesn't mater if the code uses a case or an if-elsif structure the result is the same.

But writing multiplexers (which is what you are doing) should be done using a case statement.
 

This is the compiler being non-idiotic...
 

If you need priority use "if-else" else use "Case". "if-else" is not same as "Case", not sure why the synthesis result is the same.
 

If you need priority use "if-else" else use "Case". "if-else" is not same as "Case", not sure why the synthesis result is the same.
Click to expand...
ads-ee explained in post #4 why "if-else" is exactly the same under the given conditions. If you read the explanation, which part is wrong in your view? For which value of sel do you expect different Y output?
 

If you need priority use "if-else" else use "Case". "if-else" is not same as "Case", not sure why the synthesis result is the same
Click to expand...
Under the correct circumstances (see ads-ee's note about mutually exclusiveness ) an if-else will synthesize to exactly the same logic as a case statement with all routes covered.
Perhaps, you can find a 1945 synthesis tool that would implement different logic with both code constructs - but today's synthesis tools are old enough to know better...
 

What happens if I change my priority in the "if-else" statement? Will two "if-else" statement with different priority synthesize to same logic ?
 

What happens if I change my priority in the "if-else" statement? Will two "if-else" statement with different priority synthesize to same logic ?
Click to expand...
Yes, it would.
It would, yes.
 

Difference between priority encoding and case example.

If we have a one hot select that can select one of four inputs a, b, c, and d, then the selects are mutually exclusive.
Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14

process (s0, s1, s2, s3, a, b, c, d)
begin
  if (s0 = '1') then
    y <= a;
  elsif (s1 = '1') then
    y <= b;
  elsif (s2 = '1') then
    y <= c;
  elsif (s3 = '1') then
    y <= d;
  else
    y <= 'x';
  endif;
end process;

This results in a priority encoder as there are 16 possible combinations of values that the s0-s3 can take.

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12

process (s0, s1, s2, s3, a, b, c, d)
  variable sel : std_logic_vector(3 downto 0);
begin
  sel := s3 & s2 & s1 & s0;
  case (sel) is
    when "0001" => y <= a; 
    when "0010" => y <= b; 
    when "0100" => y <= c; 
    when "1000" => y <= d; 
    when others => y <= 'x'
  end case;
end process;

Without verifying, I believe this will result in an equation like this:
Code VHDL - [expand]
1

y <= (a and sel0) or (b and sel1) or (c and sel2) or (d and sel3);

Which is a non-priority encoded circuit where sel0-3 must be mutually exclusive.l
 

ads-ee said:
If all the selections are mutually exclusive and all possible selections are defined then it doesn't mater if the code uses a case or an if-elsif structure the result is the same.

But writing multiplexers (which is what you are doing) should be done using a case statement.
Click to expand...

A multiplexer select input is mutually exclusive in all the possible selections and all the possible selections are defined. Why should we write the multiplexer code using case statements only?
 

Unlike in Verilog, case statements in VHDL are supposed to infer mutually exclusive "cases", which is why they are preferred over if-elsif-else structures (where a mistake can leave you with a huge priority encoder).

But if you insist on doing it with if-elsif-else structures then go right ahead, but you'll probably be forced to change your coding style after your first code review and/or design review.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top