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comparator simulation question

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dayang

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Hi,every one;
now I want to evaluate the performance of a latched comparators which has two stage preamp and a dynamic lach stage and I want to know how to simulation the key parameters of this type of comparator such as: offset, resolution, overload revovery,speed(bandwidth) and so on. Can anyone give me some advise or some atricle on how to do it? I have read some article about it but still have no idea on it.

Best regards
 

help anyone help me on this topic?
 

Draw the schematic, and give in detail of what do you want to happen.
 

the latched comparator is a typical architecture consist of a preamp(two stage) and
dynamic latch.what I want to know is how to evaluate the performance of it ust the spice simulation,thank you.
 

for offset, you need to manually tweak your transistor sizes, making them hard to sense your input differential; for resolution, you just add an ac input signal whose amplitude depends on your ADC's bit; for overdriver load, you need to feed your comparator with a chain of 1s (or 0s) followed by a single 0(or 1) which is followed by a series of 1s (or 0s), you need to see whether your comparator can recover from a long series of 1s (or 0s); slew rate, you just need to measure your output signal's slew rate with output loading. worst offset should be applied to all these simuations
 

can u really simulate the offset? it is dependent on the process and your input transistor size, isnt it?
 

Yeah, you should have a spec about how you transistor W/L varies, or better, you can get a statistical model for your transistor
 

You should make monte-carlo simulations, you can find it in other topic!
 

i think mente-calo analysis is more suitable for comparator offset simulation.
 

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