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the main component that affect the pll bandwidth is thwe loop filter ,
when u design the loop filter u must ensure that the bandwidth of the loop is less than the reffernce frequency ur using "linaer approximation validity "
about simulation u can simulate thwe pll system using matlab in the phase domain whcih u can get step response bandwidth . stabillty
also u can simulate it in time domain
thanks ,i have a question,does the bigger the bandwith of pll,the faster lock-time of pll?and I dont konw how to use matlab to simulate a pll with loop filter,are there any component like resistor and capital model in the matlab as cadence ,can you give me a matlab sample ,or i just should konw the transfer function of the loop filter?
yes as the bandwidth of the pll increase the speed of the pll increase or the lock time decrease
about the simulation in matlab insted of the componnet use the transfer function of the filter in s domain "but it as ablock " the VCO model is integrateor multiplied by a constant "the KVCO"
big bandwidth also means your pll will see more noise from your input.
You have to balance lock time, jitter for your specs. Also your bandwidth has to be small comparing with your output frequency otherwise your linear approximation of PLL may not work well
yeah
and u can use a low jetter refernce oscillator
but also as the divider increase it is value will be multiplied with the phase noise of the crystall "amplify the phase noise "
so u must know what u need from pll and compromise loop parameters
Is the bandwith of pll definded maianly by the bandwith of loop filter ?why shuold the bandwith of pll be lower than the frequence of the refernce ,noise consideration?
i think the loop bandwidth will determine the aquisition range of the pll.if u try to reduce the ripple in the vco control voltage by lowering the loop bandwidth and rejecting high frequerny components then the aquisition range suffers.this is because the range of frequencies for which the pll locks is determined by Win-Wdiv<WLPF.
The bandwith of a pll roughly equals to Icp*Kvco*R/2*Phi*N
where Icp is the current of Charge pump, Kvco is the gain of vco, R is the value of resistance in a 2 order loop filter. N is the ratio of the divider.
so if you want to enlarge the bandwith, you can increase the value of R. But you cnanot increase the bandwith too large. It's a lemma that the bandwith should be smaller the 1/10 of the input frequency to avoid instability.
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