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Reducing the noise in analog circuit with layout technique

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ambreesh

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layout and noise

Help me here please.
Can we reduce the noise in an analog circuit by use of certain layout techniques.
If yes could someone please elaborate on the same.
for example how could flicker noise be reduced by certain type of layout. etc
 

Re: layout and noise

If you meant device noise, you want to use standard geometry devices as they are well described by spice model. This is what's model for. If you deviate from the common geometry, the model becomes incorrect. Then you might or might not get some noise advantage, but all your currents, voltages, gm, etc are not modeled also. You are in completely unknown territory.
On the other hand, if you go to this territory anyway, please let us know. I'm working under constant schedule constrains, and I have zero time for such experiments. But I welcome any brave soul who can test these unknown waters for all of us, overconstrained designers.

If we talk about noise coupling via supply or substrate, it can be reduced by good differential layout with many guard rings and triple well isolation.
 

Re: layout and noise

Dear Steer,
Offset is a noise.
I have read a paper by Dr A B Bhatacharya in which he has shown that by matching some unrelated devices the offset can be reduced.
I shall upload it if u need to go through it.
As for the substrate noise reduction, majority of work has shown that till u donot have the back plane of the die tied to ground all isolations show more or less the same effect for higher frequency substrate noise. And with fast switching digital on mixed signal chips everything is as good as a psubstrate guard ring at higher frequency.
 

Re: layout and noise

Well, good layout can reduce systematic offset, in part caused by area gradients, edge effects, etc.
Random portion of offset is not really reduced by layout.
The flicker noise behaves similarly to random offset component in that respect.

As for the substrate noise and such, guard rings can be done in a different fashions. Not all of them are effective.
And even in best case, their effectivity is limited, just like you mentioned. Still, a correctly made guard ring is better than nothing.
 

Re: layout and noise

Dear Steer,
I agree with u that some guard ring is better than nothing. I am not againts guard rings. All of use them.
Have u come across certain thumb rules for various technologies that would tell about usual width of guard ring. Please share the data if u have some.
Also i was told that if u have substrate contact' in 0.35µ technology at max distance of 10µ from each other it is good.
Do you have any data on the same.
Over what small area on wafer do the local parameters do not change, does it depend on the the technology. Have u come across something like this. The paper I mentioned in earlier responce talks of such area a 100µx100µ
I will upload the paper u would surely enjoy it
 

Re: layout and noise

Guard ring strategy depends on process used. Epi process requires guard rings placed as close as possible to the sensitive devices. Non-epi process is more forgiving to the distance to guard ring, but it is sensitive to guard ring thickness. The thicker it is, the better. SOI process is yet another completely different story.

What is your process? 0.35um processes exist in all these flavours.

As for the area where gradient is small, it depends on process and devices used. If your device is 0.2um^2 small, it has large random variations that mask area gradients. Then you can space such deveices 500um apart and still remain random mismatch dominated. On the other hand, if you have 100um^2 large devices, their random mismatch is small, so at 100um distance the accumulated gradient dominates the mismatch.
Any reputable fab I know of provides mismatch characterization data. Being under NDA I can not share my data with you, but you can ask your fab for that.
 

Re: layout and noise

The process I used was N-Well digital Cmos process.
 

Re: layout and noise

ambreesh said:
The process I used was N-Well digital Cmos process.
Click to expand...

Does it have epi layer?
 

Re: layout and noise

No we have no epi layer.
 

Re: layout and noise

OK, no epi process gives us few choices.
One strategy can be to take with p+/pwell guard rings as large area as possible, as current spreading resistance is proportional to area. This is a good choice when digital portion is small. Then whole the substrate can be made quite.
Other strategy is to place small p+ guard rings as close as possible to each analog transistor. Then we give up with whole substrate potential control, but control local substrate potentials close to each transistor. This is a good way when analog content is small and chip is mostly digital.
 

Re: layout and noise

Dear Steer,
As u have mentioned we have used both the guard rings for the safety puorpose, but never had any idea on the widths of the guard rings. And still donot.

To maintain the local potential constant (guard ring around each transistor), what is the maximum distance between the substrate contacts onthe same guard ring.

How benefecial is it to have an N+ guard ring around a P+ guard ring. (we talk of N-well digital CMOS with no epi layer). Substrate current is not a surface phenomenon and usually they flow far below the depth of N-well.
 

Re: layout and noise

ambreesh said:
Dear Steer,
As u have mentioned we have used both the guard rings for the safety puorpose, but never had any idea on the widths of the guard rings. And still donot.
Click to expand...

If one pursues local guarding strategy in no-epi process, the guard ring width is about twice of distance between mos under protection to the guard ring. This is for best noise protection. It costs a lot of area though. Most designs I've seen make some resonable trade-offs between protection quality and area.

ambreesh said:
To maintain the local potential constant (guard ring around each transistor), what is the maximum distance between the substrate contacts onthe same guard ring.
Click to expand...

For small guard rings the current spreading resistance can easily be 1K or more. In such a condition one contact would suffice. Large guard rings require more contacts. One per 5-10um looks good enough to me. Again this is only true for no-epi process.

ambreesh said:
How benefecial is it to have an N+ guard ring around a P+ guard ring. (we talk of N-well digital CMOS with no epi layer). Substrate current is not a surface phenomenon and usually they flow far below the depth of N-well.
Click to expand...

You are right, N+ guarding is just a waste of area in your p-substrate no-epi process.
 

    A

    ambreesh

    Points: 2
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layout and noise

What about P+ guard ring in p-substrate no-epi process?
 

Re: layout and noise

yeechyan said:
What about P+ guard ring in p-substrate no-epi process?
Click to expand...

This is the most effective way to protect analog circuits. Actually, most of the things we discussed above are about P+ guarding.
 

Re: layout and noise

Dear yeechyan,
Majority of work done till date on the area of reduction in noise shows that P+ Gurad ring is the best choice for suppressing high frequency noise. As all others show the sam e behaviour as this so why use extra mask.
Only exception to this is when we could ground the back plane of the die in triple well isolation process.
Some of the studies have shown that at times certain guard ring (other than P+) could have a deteriorating effect also.
Steer has very good idea on this. He has cleared a lot of my doubts too.
 

Re: layout and noise

I suggest using "star" power & GND.
On the n+ guard rings , add nwell , with a width 2x as wide as minimum.
the minimum width does not let the nwell go as deep as a wider width.
Tie the N+/NWELL to positive supply .. ie: Analog power.
 

Re: layout and noise

Dear Cadenceguy,
Are u sying that the Power and Gnd should be distributed in Star fashion or something else in your first line.
secondly, I donot understand how would and what % extra would using 2x width of Nwell increase the depth of Nwell, the concept is not clear.
thirdly, I have come across no work that says or proves that N+/Nwell guard ring would be superior to P+ guard ging at high frequency, If you have some data , please share.
 

Re: layout and noise

Ambreesh,
If you are trying to seperate a noisy area from a quite area
then each should have its own route back to the pad.
Unless of course you have multiple power pads.
Dont use the same GND-metal to connect noisy areas with quite areas
even though they connect thru substrate.

The minimun nwell width does not allow the nwell to down diffuse as far.
so look here (topographical)

Noisy-Psub | NN | quiet-Psub

Do you see a LPNP ?
Tie the base High .. This is also known as a "hole-injection-Guardring"

The inductance of the substrate is in your favor now.
 

    A

    ambreesh

    Points: 2
    Helpful Answer Positive Rating
Re: layout and noise

Dear Cadenceguy,
Correct me if I am wrong, The NW whch is base of LPNP reverse biases the CB and EB diode. Thus decreasing the capacitance and in turn reducing the coupling.

What is this substrate inductance. Are u talking of the subsrate inductance on the noisy substrate side.
Could you elaborate on the functioning of this inductance. I am not clear.
Eles if you have some data on the same you could please share it. I could go-through the same and then come back with my doubt and/or understanding
 

Re: layout and noise

1/f noise could be eliminated by the use of PMOS transistors for the input in the case of diff amps..
 

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