Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Saturated CMOS Inverter problem.

Status
Not open for further replies.
cannibol_90

cannibol_90

Member level 5
Joined
Jun 20, 2009
Messages
83
Helped
5
Reputation
10
Reaction score
5
Trophy points
1,288
Activity points
2,066
Saturated NMOS Inverter problem.

Hi,

I was trying to simulate a nMOS saturated inverter in AWR AO.

nmos saturated inverter.jpg

1. The bias voltage in the attached figure is 5V. But the inverter gives an output of 2.5V. In contrast, a CMOS inverter gives an output voltage of 5V. Why is it that so?

saturated inverter VDC.png

2. As Gate and Source are shorted, the upper nMOS is is always in saturation. If the output voltage is fixed at 2.5V, does it mean that the threshold voltage of the upper nMos is 2.5V?

Vds = Vgs - Vt

Vds = -Vt ( As Vg = Vs)

By KVL (Vdd to ground) : Vds = 2.5

Hence Vt = -2.5V??? (for nMOS???)


HELP???

- - - Updated - - -

Also I need to know whether a CMOS inverter gives more or less propagation delay than an ordinary NOT Gate.
 

Re: Saturated NMOS Inverter problem.

cannibol_90 said:
1. The bias voltage in the attached figure is 5V. But the inverter gives an output of 2.5V. In contrast, a CMOS inverter gives an output voltage of 5V. Why is it that so?
Click to expand...
See item 2

cannibol_90 said:
2. As Gate and Source are shorted, the upper nMOS is is always in saturation. If the output voltage is fixed at 2.5V, does it mean that the threshold voltage of the upper nMos is 2.5V?

Vds = Vgs - Vt
Click to expand...
No: Vds = Vgs = Vt + Vod ; Vod = Voverdrive is the voltage additional to Vt , which is necessary to allow for the Ids current of the upper side NFET, which is sunk by the lower side NFET.

cannibol_90 said:
By KVL (Vdd to ground) : Vds = 2.5 ; Hence Vt = -2.5V??? (for nMOS???)
Click to expand...
No: Vds = Vt + Vod , so Vt could be +1V and Vod = +1.5V .

cannibol_90 said:
Also I need to know whether a CMOS inverter gives more or less propagation delay than an ordinary NOT Gate.
Click to expand...

Prop. delay for output falling should be about the same (depends mainly on the W/L ratio of the lower side NFET). For rising output, prop. delay of the NMOS inverter will be longer than for a CMOS NOT gate, because the "diode connected" upper side NFET usually provides less current than a full power supply controlled PMOS with same W/L ratio.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top