Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] MOS device parameter range in HCMOS 9GP (130nm) !

Status
Not open for further replies.

ranaya

Advanced Member level 4
Joined
Jan 22, 2012
Messages
101
Helped
4
Reputation
8
Reaction score
9
Trophy points
1,298
Location
Kelaniya
Activity points
2,164
Hi all,

I've got a question about the MOS transistor length range in HCMOS 9GP 130 nm technology. I've implemented a current mirror circuit for SAR ADC with high speed transistors. The problem I have at the moment is I cannot increase the high speed transistor length beyond 0.4u in cadence simulation. Here simulation in the sense, I cannot directly apply that larger L value to the transistor properties. But in specter, the dc sweep of currents over length of transistor is possible for larger length values (>0.4u). According to both model file and design rule manual, the Lmax is set to 0.4u.

But in order to obtain 0.5 LSB accuracy in current mismatch, at least the L should be increased to 3u (have tried many current mirror topologies). So if the model does not accept that value, does it mean that the above mentioned technology cannot process a transistor with larger L values (let's say 3u) ? Or is it only for the sake of simulation ? Any explanation will be appreciated !

Thank You
 

Probably You are using RF fets which has limitation in layout to be not longer than 400nm. For modelling it is not a problem if You will use standard fets which allowing longer lengths.
 

Max. length (and/or width) limitations only apply for the validity of model accuracy. Actually there's no physical reason for an upper limitation (apart from area consumption); you can in fact design and layout longer (and wider) transistors. Just the accuracy of your analysis results (regarding absolute current value accuracy) aren't guaranteed, but it doesn't concern mismatch (because this one improves with 1/√area).
 
  • Like
Reactions: ranaya

    ranaya

    Points: 2
    Helpful Answer Positive Rating
Hello all, thanx for your replies.

Yehh even according to the current mismatch equation (Pelgrom model), the mismatch performance should be improved by the larger L. So it seems like the Lmax is only defined for the transistor model validation. Anyway when I checked the "moshs" model file, I noticed the same Pelgrom model has been defined as the drain current mismatch equation.

A doubt:
So if it does not concern mismatch then the spectre (ADE) mismatch simulation for larger Ls should be accurate right ?
Or it's not since the current values will not be guaranteed ?
 

Model doesn't guarantee accurate drain curent for L in order of tens of µm, for L=1..10µm it shouldn't be a problem
 
  • Like
Reactions: ranaya

    ranaya

    Points: 2
    Helpful Answer Positive Rating
... when I checked the "moshs" model file, I noticed the same Pelgrom model has been defined as the drain current mismatch equation.

A doubt:
So if it does not concern mismatch then the spectre (ADE) mismatch simulation for larger Ls should be accurate right ?
Or it's not since the current values will not be guaranteed ?

Yes, mismatch calculation should be ok for larger Ls. Possible inaccurate drain current results have no effect on mismatch calculation.
 
  • Like
Reactions: ranaya

    ranaya

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top