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Interview question: MOS Biasing related

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cczztt

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I was asked that there is a nmos with Vth=1V, gate voltage Vg=3V. One end of the nmos node B (source/drain) is connected with a small capacitor (almost instantly charged), and the other end node A (source/drain) is swept from 0V to 3V.

Question: How is the voltage at node B changed as node A ramping from 0V to 3V?

Thanks ahead for answering my question.
 

SunnySkyguy said:
What was your answer?
Click to expand...

I answered that as node A ramp from 0 to 2V, the nmos is on, and Vgd=Vth, the voltage on node B should be Vth lower than the gate voltage, so node B will be 2V. (However, I always confuse that why Vgd will stay equal to Vth, I know that Vgd<Vth for saturation, and Vdg>Vth for linear region). As node A ramp from 2V to 3V, node B become the source, and node B stay at 2V in order keep the nmos on. So the voltage at node B is always 2V.

I am not sure if my answer is correct or not. And I always confuse about the value for Vgd.

Look forward to your feedback.
 

I am not sure if I understand the question, but as I see it the transitor will be in linear/triode mode until Vgs>Vth and Vds<(Vgs-Vth). If this is true node B will more or less folow node A.

BR Jerry
 

do we need to know the initial condition of cap? or you assume it is 0V at time 0 ?
 

The reference or common points are a bit vague. but if we say Vgs =3V regardless of node A or B then they were be equal since the FET is conducting easily.
 

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