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Hole in LNA pcb under fet transistor to reduce inductance.

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Terminator3

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What mechanism stays behind this method? Is it only to provide good grounding in common source amp or smthing else. Its a huge hole, not via. I think it is plated.
 

It seems that this "large via hole" is designed for minimum path length to ground. The only way to reduce RF inductance is to keep the path as short as possible, so it would make sense.

Using many vias at different distances is quite useless because vias with a longer path have almost no effect on total inductance at RF frequencies.
 
What if we solder source pin directly to ground plane on the other side of pcb? Although need to put vias on gate and drain, i can imagine gate and drain can be coupled to waveguides without vias. For high gain amplification and still stable solution
 
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To clarify my previous post i must add that good grounding of source pin makes easy use of s-parameters given by manufacturer. If VNA is available it is not a big problem. (Adding inductance to source pin can move things far away and stability circles would be wrong)
 

Terminator3 said:
To clarify my previous post i must add that good grounding of source pin makes easy use of s-parameters given by manufacturer.
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Understood, but measured S-parameters by the manufacturer also include some source length (as short as possible with optimum via location and thin PCB).
 
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