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Re: what is the key reson for scaling gate oxide thickness d
With decreasing feature size we donot have concept of one dimensional feild, but we have 2D field effect.
The drain starts to have conciderable effect/ influence. (DIBL)
To have more coupling through gate and thus stonger and predominat gate control over the device, the gateoxide thickness is decreased 9larger capacitance)
Hope it helps
"When reducing the gate length of an MOS transistor, the depletion regions around the source and drain have also to be reduced, to avoid effects such as charge sharing and punchthrough. To scale down the depletion regions, the doping oncentration of the substrate can be increased and the biases applied (i.e. the supply voltage) can be reduced.
The increase in the substrate doping also increases the threshold voltage, and this makes it more difficult to turn on the device. To compensate for this the gate oxide thickness is reduced."
Re: what is the key reson for scaling gate oxide thickness d
From the device model point of view, the decrease of gate oxide always improves the mobility of the device, which tends to make the device ft even higher (or faster).
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