vovan76
Junior Member level 3
Hi
I need to design LDO which will work also for retention mode where SPEC for self current is very low.
For regular mode Iself <800u
For low power mode Iself<10u
Somebody have an expirience for such kind of design?
Lets say i can design high power amplifier and switch it for low power mode - but during the switching LDO output volatge can jump up /fall down and go out from SPEC limits
BTW i have an option to design such LDO with NMOS pathgate (OTA has option for higher VDD )
Thanks
I need to design LDO which will work also for retention mode where SPEC for self current is very low.
For regular mode Iself <800u
For low power mode Iself<10u
Somebody have an expirience for such kind of design?
Lets say i can design high power amplifier and switch it for low power mode - but during the switching LDO output volatge can jump up /fall down and go out from SPEC limits
BTW i have an option to design such LDO with NMOS pathgate (OTA has option for higher VDD )
Thanks