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[SOLVED] DRC error that I can't understand

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AMSA84

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Hi guys I have an error that I can't understand why is happening:

error_cadence.png

It is the first one. This kind of error has to do with the contacts to the NWELL. I had this error before, but not for this kind of layout (mosfet that will serve as power devices).

As you can see I have the contacts to the well but he still gives the error. The description on the right I never saw before.

Does anyone knows why this is happening?
 
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If that's all one big NWell and only contacted about the
periphery, there may be regions where you violate the
tap-to-channel distance rules or something like that
because your device is too big without intervening taps.
 
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