omigaagimo
Newbie level 4
I am stucked at the middle of some complicated design.
I need some kind of automated method for measuring system different input transistion delay. as there are to many IO ports in my design it would be a very big help, if I find an automated method for cadence software suite.
Is there any kind of input waveform generator for digital chip simulation available in Cadence? Something like what we can utilize in other software like Quartus or Active HDL?
Or Is there any GUI based method for desiging custom waveform with PWL. I found some kind of ocean script but its rather complicated!
I have to simuate multi input output digital chip and measure different transitions delay for finding system worst case delay! If I just rely on transient simulation, I probably would make alot of mistakes!
I need some kind of automated method for measuring system different input transistion delay. as there are to many IO ports in my design it would be a very big help, if I find an automated method for cadence software suite.
Is there any kind of input waveform generator for digital chip simulation available in Cadence? Something like what we can utilize in other software like Quartus or Active HDL?
Or Is there any GUI based method for desiging custom waveform with PWL. I found some kind of ocean script but its rather complicated!
I have to simuate multi input output digital chip and measure different transitions delay for finding system worst case delay! If I just rely on transient simulation, I probably would make alot of mistakes!
