PMOS radiation hardness?

Why are PMOS-Transistor more insesetive against radiation?

In what respect are they more insensitive?
Radiation causes charge build-up in the gate oxide, changing the transistor's threshold voltage.

But for PMOS, it is a different case. Because PMOS transistors
are built on an n-type substrate, the positive trapped
charges caused by radiation cannot deplete or inverse the ntype
substrate. As a result, after radiation the magnitude of the
threshold voltage of the parasitic transistors will not be reduced
and the 1/f noise will not increase. That is the reason why
PMOS transistors are more resistant to radiation damage than
NMOS.

Click to expand...

**broken link removed**

Why does the radiation and the creation of positive charged charges not change the potential of the n-substrate?

They are nothing of the sort. In fact most active electronic
gamma dosimeters are PMOSFETs "optimized" for the worst
VT shift you can get.

I once worked on a process development where we were
happy to get "only" -4V VT shift on the PMOS, while the
NMOS shifted "only" 2V or so.

PMOS is worse in terms of gross in-application VT shift
because its direction of VT shift and the subthreshold
drag-out (surface states) are additive, while in NMOS
they cancel (until you anneal it and rebound, anyway)
to some extent.

PMOS does fare better against the LOCOS / STI edge
leakage than NMOS. But this is not the active device
per se, it is the isolation -becoming- active when you
would like it to STFU. Field oxide VT shift (charging)
turns on P-field and turns off N- field. You can fix that
with hardened field oxides, implants or device geometry.

This is what the linked paper is showing, it has nothing
to do with the explicit channel and everything to do with
using a process and device construction that isn't up to
the job. You shouldn't generalize it beyond that.