Timing Constraints: are there any "design patterns" indicating good practice?

Timing Constraints: are there any "design patterns" indicating good practice?

I'll shortly be starting a design in a Zynq FPGA using Vivado. I'm confident that I will be able to use VHDL to create the design, partly because it isn't outside my comfort zone, and partly because there are many app notes/tutorials/books etc on that subject. Timing constraints are a different issue, mainly because they seem to be relatively neglected and un-glamorous.

What I would really like are some examples of "good practice", i.e. small self-contained examples using timing constraints, documenting what is necessary and what is sufficient, and why. I emphasise "small and self-contained" since at this stage I'm not interested in all the arcane possibilities of the constraint languages, merely the common cases with their boundaries. In the software community such things have been given the somewhat fancy name of "design patterns", but it is a valuable concept.

So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.

Background is that the logic design will be conventional, with patterns based around

• blocks containing FSMs in the form of one VHDL process for the combinatorial logic plus another VHDL process for the registers
• two (or more!) clock domains, some with period X, some period 8X (i.e. a nice simple integer relationship)
• re-synchronisation across those domain boundaries, using predefined standard Xilinx FPGA primitives
• external i/o timing is, perhaps surprisingly, "don't care"; I'll resynchronise inputs myself, and will accept whatever the outputs provide
• and I'm presuming that the PL<->PS interface will be "dealt with" by Vivado without my intervention

So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.

Re: Timing Constraints: are there any "design patterns" indicating good practice?

tggzzz said:

• blocks containing FSMs in the form of one VHDL process for the combinatorial logic plus another VHDL process for the registers

Click to expand...

use a single process FSM, you're less likely to make a latch mistake.

• two (or more!) clock domains, some with period X, some period 8X (i.e. a nice simple integer relationship)
• re-synchronisation across those domain boundaries, using predefined standard Xilinx FPGA primitives

Click to expand...

Uh, what synchronization primitives? If you're using a PLL/MMCM then any output clock that is an integer multiple of another output clock will be timed correctly to allow synchrnous transfers between the clock domains without a syncrhonizer. The only issue you have is the transfer has to meet setup/hold of the faster clock as the launch and capture edges will be from/to the faster clock and the slower clock.

• and I'm presuming that the PL<->PS interface will be "dealt with" by Vivado without my intervention

Click to expand...

what do you mean by PL and PS?

So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.

Click to expand...

Look for a timing constraint document on Altera's forum it's in their FAQ, that document does a pretty good job of showing you how to write timing constraints in SDC, which work for XDC. There are a few gotchas where there are some commands for propagating clocks that aren't required (and don't exist) in XDC.

I also recommend reading the Vivado Design Suite User Guide, Using Constraints, UG903. It give you simple examples and tells you most of what you'll need.

Re: Timing Constraints: are there any "design patterns" indicating good practice?

ads-ee said:

use a single process FSM, you're less likely to make a latch mistake.
what do you mean by PL and PS?

Click to expand...

Zynq terms: PL = programmable logic (i.e. the FPGA fabric), PS = processing system (i.e. the dual-core ARM)

Look for a timing constraint document on Altera's forum it's in their FAQ, that document does a pretty good job of showing you how to write timing constraints in SDC, which work for XDC. There are a few gotchas where there are some commands for propagating clocks that aren't required (and don't exist) in XDC.

I also recommend reading the Vivado Design Suite User Guide, Using Constraints, UG903. It give you simple examples and tells you most of what you'll need.

Click to expand...

Thanks for the pointers. I'm aware of UG903, and will follow up on the Altera FAQ.

Re: Timing Constraints: are there any &quot;design patterns&quot; indicating good practice?

Actually I can't seem to find that document that a Altera forum member wrote, I also couldn't readily find my copy of the pdf...

I did find the following: https://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf
and what looks like something that might help write sdc (a.k.a. xdc) files.

- - - Updated - - -

Took a bit of searching but found it. . It's basically a user guide for TimeQuest but as timequest uses SDC and the doc describes how to use TimeQuest to enter constraints...so you get to see how to constrain a design, which can be applied to Xilinx Vivado as well.

Re: Timing Constraints: are there any "design patterns" indicating good practice?

tggzzz said:

• blocks containing FSMs in the form of one VHDL process for the combinatorial logic plus another VHDL process for the registers

Click to expand...

• 
  
  Come into the 21st centuary and use single process state machines
  
  

  [*]two (or more!) clock domains, some with period X, some period 8X (i.e. a nice simple integer relationship)

  Click to expand...

  
  While you could use integer multiple clocks that should have safe timing, Id probably go with a FIFO for this - it makes the control logic for you. Plus the core gen may create the SDC or template SDC files for you.
  
  

  [*]re-synchronisation across those domain boundaries, using predefined standard Xilinx FPGA primitives

  Click to expand...

  
  The only library synchronisation module I know of is a FIFO. Anything else, you'll have to make yourself.
  
  

  [*]external i/o timing is, perhaps surprisingly, "don't care"; I'll resynchronise inputs myself, and will accept whatever the outputs provide

  Click to expand...

  
  I hope you dont intend to resynchronise by using logic to create different delays? very very bad practice. Much easier to provide timing constraints and use the IO delay lines and fast IO registers provided at the pins for you.
  
  

  [*]and I'm presuming that the PL<->PS interface will be "dealt with" by Vivado without my intervention

  Click to expand...

  
  Yes and no. As long as you use system generator it will be done for you. BUt you still need to provide the SDC files for the clock sources.
  
  

  So, I'd be grateful for pointers to references that you found useful when you were learning how to use constraints effectively.

  Click to expand...

  [/quote]
  
  The Altera Timequest guides are good (because they've been using SDC for about 5 years!)

Timing Constraints: are there any "design patterns" indicating good practice?

ads-ee said:

Actually I can't seem to find that document that a Altera forum member wrote, I also couldn't readily find my copy of the pdf...

I did find the following: https://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf
and what looks like something that might help write sdc (a.k.a. xdc) files.

Took a bit of searching but found it. . It's basically a user guide for TimeQuest but as timequest uses SDC and the doc describes how to use TimeQuest to enter constraints...so you get to see how to constrain a design, which can be applied to Xilinx Vivado as well.

Click to expand...

Thanks for taking the time to find the URLs. The first one in particular is helpful, and "cookbook" is a good search term that I haven't used in a while

Re: Timing Constraints: are there any "design patterns" indicating good practice?

TrickyDicky said:

Yes and no. As long as you use system generator it will be done for you. BUt you still need to provide the SDC files for the clock sources.

The Altera Timequest guides are good (because they've been using SDC for about 5 years!)

Click to expand...

Thank you for the pointers.

OT: is there any way of "quoting" a reply that retains the full context, i.e. two or more levels of quotes? It is rather limiting not to be able to see what your "yes and no" answer was referring to!