virtual ground at inverting terminal of opamp in switched capacitor amplifiers

hello everyone !!!

I am reading the chapter on switched capacitors "Design of analog integrated circuits " by Razavi.

In the case of SC amplifiers, what maintains a virtual ground in the amplification mode??? (since no DC feedback is shown)
https://obrazki.elektroda.pl/8342746700_1420399368.png

I too have the same doubt !!
when the switch is closed in the sampling phase virtual ground is maintained. But, what happens in the amplification phase(hold phase).

Circuit (a) is simply a voltage follower unity gain with AC coupling due to effective input resistance R ( big) and series input Cap, C , T=RC. THe result is DC or low frequency blocking and output will be at same DC voltage as (+) in this case ground.

Circuit (b) is an AC divider amplifier just like a resistive divider amplifier except it has no DC reference so additional circuits must switch the feedback cap to null any offset. THis design is used for piezo capacitive accelerometers where the charge generated from vibration is amplified by the C ratio (Cin/Cfb) and presents a high impedance to the piezo device.

I have no idea what the author was trying to demonstrate for (a) as sampling mode because there is no sample and hold switch.
In (b) the amplification mode is shown for the step response but actually the input RC filter response for the input bias current and effect resistance and hence LPF effect shows the time response, but above this frequency breakpoint the AC frequency response is flat gain.

Both circuits show euqivalent diagrams for two different time slots.
(a) for the sampling mode (first half of the clock period) the feedback cap is shorted and the input cap C1 is charged to the instantaneous value of the input voltage.

(b) in the second half of the clock period the charge is transferred to the feedback cap C2 (amplification mode) . There is no need for an additional dc feedback because C2 provides a feedback path. You cannot explain S/C circuits using the terms DC and/or AC. However, during the short transfer time slot you can treat the feedback current as (nearly) DC. At the beginning of this period, the capacitor C2 (discharged) even provides a short circuit.
Hence, the inverting opamp terninal can be considered to assume virtual ground potential.
Because of C2<C1 we have V(C2)>V(C1).

An excellent explanation can be found in this lecture

**broken link removed**