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Warns me: Xst:2170 - Unit arbitter: signal(s) form a combinatorial loop

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rekhavp

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Hi all

While simulating a NAND latch the following warning is produced. HOW can I eliminate this?
WARNING:Xst:2170 - Unit arbitter : the following signal(s) form a combinatorial loop: Q.code is also attached with it.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity arbitter is
    Port ( P,S : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end arbitter;
 
architecture Behavioral of arbitter is
SIGNAL r,rbar: STD_LOGIC;
begin
rbar<=P nand r;
r<=S nand rbar;
Q<= not rbar;
end Behavioral;
 
Last edited by a moderator:

You can eliminate this by removing the combinatorial loop.
You've created a latch from logic gates. The problem is a real system has some delay through the gates, so you will get oscillation in the Q output.

So the answer is - dont create logic loops in real hardware.
 

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