naijacoding
Newbie level 1
Hello all. I'm new to VHDL programming so please forgive me in advance if i ask any bad question. I have an assignment to create a VHDL model and testbench for SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT device. I have started reading up as much as i can and time is running out. Could i get ideas, advice or any help on this topic? thanks