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Quick Verilog question

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vlad928

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I have a wire that I want to assign to my output. I have tried using x1 = out1 and it gives an error. Here is a pseudo code of what I am talking about.

Code Verilog - [expand]
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module test (out1, in1);
output out1;
input in1;
wire x1;
 
not (x1, in1);
 
wire x1 = out1;
 
endmodule
 
Last edited by a moderator:

the 8th line is incorrect.. you must replace "wire" with "assign".
 
It should also have the x1 and out1 swapped.
Code: 
assign out1 = x1;
 
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