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Problem with behaviour description of IIR filter in VHDL

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smith_kang

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vhdl help

hi all
i've written a behaviour description og IIR filter in VHDL and use
wait on clk until clk='1'
during synthesis with xilinx it is giving error and expecting exit after wait.is this neccessary to give this.in compilation there was no error in the code.
kindly give your valuable suggestions
 

Re: vhdl help

Hi,
Why dont you use standard coding style instaed of wait statements.
You could have used standard sequential process.

Code: 
process (clk, reset_n)
  begin
        if (not reset_n) then

        elsif (clk'event and clk = '1')

        end if;
  end
 

Re: vhdl help

hi
thanks for reply.but i've not used sensitivity list in process.process doesn't have any sensitivity list so i used wait statement.and in IIR filter i think we don't have to include clk in sensitivity list
 

vhdl help

Hi smith,
clk signal has to be mentioned in the process sensitivity list since u r doing a sequential design.
 

Re: vhdl help

Can you post ur code here. So that I will correct it and post the corrected
code here.
 

vhdl help

main_loop:loop
wait on clk until clk='1';
lad_coeff:for i in 2*order downto 0 loop
coeff_prog(i):=coeffin;
wait on clk until clk='1';
end loop;
new_coeff<='0';
wait on clk until clk='1';
filter:for i in count-1 downto 0 loop
hshk_loop:while(enable='0') loop
wait on clk until clk='1';
end loop;
 

vhdl help

Hi smith_kang,
I guess the wait statements in VHDL are not synthesisable. they are used for behavioral modfelling only. Recode your logic based on standard templates provided by your synthesis tool.
 

Re: vhdl help

Sorry to say but this code is definitely not synthesizable!
HDL means "Hardware Description Language" So first you
think about the hardware and to describe it use HDL.
You seems to be new to VHDL and logic synthesis.
 

Re: vhdl help

Thanks nand_gates to remind me.I'm not new to VHDL but from last few months i was trying to implement synchronous logics.thats why.
thanks again to remind me.
 

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