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CML driver design in SiGe BiCMOS process

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prcken

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Hi,
It's my first time to design circuit by using BJTs.
I am doing a CML driver as below
Capture.PNG
This is simply modified from CMOS CML circuits, but I found it doesn't work at this point, maybe due to the base current (ib) too large? but if I make the size larger to increase beta, the speed maybe affected.

And it's easy to get this error with spectre simulation, I think it's due to improper BJT sizing?
Capture3.PNG

I read reference, there is a picture as below
Capture2.PNG
it says for (a), the input and output capacitances are vastly different. use emitter-followers to drive the input of the current swtiching pair can bring the input and output capacitances closer, like (b). input-output isolation is improved by using common-base stage at the output of the current switch as shown in (c). (d) uses another buffer stage to make the input and output capacitances of the gaincell equal.
No idea how the input and output caps can be made better for equal with emitter-followers.

Anyone had experiences in designing this? or any comments, references?

Thanks!
 
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The common emiter ciruits has poor input/output impedance, so maybe you should buffer the output of each stage or use **broken link removed** amplifier as single stage?
 

The common emiter ciruits has poor input/output impedance, so maybe you should buffer the output of each stage or use **broken link removed** amplifier as single stage?

The Rload of my circuit is small, actually.
Yep, I may should try this. But may still have problem when operating in the large-signal.
There is a comment about this topology in Razavi's book: The benefits of feedback in a Cherry-Hopper begin to diminish as the signal amplitude increases and the diff pair experiences large-signal operation. This means that the technique proves more useful in the first few stages of a limiting amplifier than in the last few.
 

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