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problem with Cycle for

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pocho

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I have a problem with the for loop.
In this piece of code I would check two vectors of length
32-bit. With the for loop control vectors bit by bit, but the problem is that in the simulation control is only in the first bit does not control the other.


Code:
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    use IEEE.std_logic_textio.ALL;
    use std.textio.all; -- utilizzo del file txt

entity testbench_adder_32bit is
    generic (T0: time:= 10 ns;
             period: time:= 200 ns);
    port (
       A, B:   out  std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32); -- li setto a 0
       Cin:    out  std_logic := '0';
       S:      in   std_logic_vector(31 downto 0) := conv_std_logic_vector(0,32);
       Cout:   in   std_logic := '0'
    );
end testbench_adder_32bit;


architecture testbench_carry_select_adder_32bit of testbench_adder_32bit is
    type test_vector_type is array (0 to 9) of std_logic_vector (31 downto 0);
    signal j: integer := 0; 
		signal k: integer := 0; 
		signal c: integer := 0;
    signal max_carry_chain:       integer := 0;
		signal semaforo:              std_logic :='0';
    signal reference_clock:       std_logic := '0';
    signal T0_clock:              std_logic := '0';
    signal T0_Cout:               std_logic := '0';
    signal T0_reg:                std_logic_vector (31 downto 0) := conv_std_logic_vector(0,32);
    signal test_vector_1: test_vector_type;
    signal test_vector_2: test_vector_type;
    signal test_vector_length:    integer := 0;
		signal A_carry, B_carry:      std_logic_vector(31 downto 0):= conv_std_logic_vector(0,32);

    begin 
        reference_clock <= not reference_clock after period/2.0;
        T0_clock <= transport reference_clock after T0;
        
        
    read_values: process
             file fp: text open read_mode is "Addizione.vhd";
             variable ln:   line;
             variable x, y: std_logic_vector (31 downto 0);
             variable i:    integer := 0;
             begin    
								 
                 while not endfile( fp )  loop --fatta modifica Menichelli
                     readline( fp, ln );
										 read( ln, x );
										 read( ln, y );
                     test_vector_1(i) <= x;
                     test_vector_2(i) <= y;
                     i := i+1;
										 end loop;
                 test_vector_length <= i;
             wait;
     end process read_values;
     
     
     input_generator: process (reference_clock)
        begin
            if reference_clock'event and reference_clock = '1' then
                if j < test_vector_length then
                     A <= (test_vector_1(j));
                     B <= (test_vector_2(j));
										 A_carry <= (test_vector_1(j));
										 B_carry <= (test_vector_2(j));
                     j <= j+1;
                elsif j = test_vector_length then
                    j <= j+1;
                	end if;
            		end if;
        end process input_generator;


------------------------------------------------------------------------
                    carry: process (A_carry,B_carry)
										 begin						
                     for k in 0 to 31 loop							
                           if       ((A_carry(k)= '1')) and ((B_carry(k)= '1')) then						 
                                    semaforo <='1';											
                                    c <=c+1;		 								  
                           elsif    ((A_carry(k)= '1') or (B_carry(k)= '1')) and (semaforo = '1') then					
                                    c <=c+1;										 
                           else
                                    semaforo<='0';
                                    c <=0;					   
                           end if;
                     end loop;
                     k<=0;
                     if max_carry_chain < c then									
	                      max_carry_chain<=c;
	                   end if;	
                     end process carry;
-----------------------------------------------------------------------


      
       
        
        write_result: process( reference_clock )
        file fpo: text open write_mode is "test_result.txt";
        variable lno: line;
        variable xo: bit_vector(31 downto 0);
        variable yo: std_logic;
        begin

            if reference_clock'event and reference_clock = '1' then
                if j/=0 and j<=test_vector_length then
                    xo := to_bitvector( S );
                    write( lno, xo );
                    writeline( fpo, lno );
										yo := Cout;
                    write( lno, yo );
                    writeline( fpo, lno );
                end if;
            end if;
        end process write_result;

end testbench_carry_select_adder_32bit;
 

you have to remember that signals are assigned only when a process suspends. So assigning
c <= c + 1;

inside your loop with no wait statements will only give you c + 1, not c + 31.
 

so there is a way to solve? (I tried to remove the sensitivity list, introducing 'wait' but does not work)
 

You need to step back and think of what you are trying to do. Your entire code seems to be pieced together without any high level design having been done.

From what I can tell based on your code you are trying to compare two 32-bit vectors and determine the most significant carry. I'm not sure why you are trying to do this using a for loop. If you want to do the operation serially use a shift register and a counter (clocked operations), otherwise use a bit wise XOR operation and a prefix sum operation (both parallel operations) to find the most significant 1 in the A_carry B_carry comparison.

I'm not entirely sure that the if statements do what you want them to do.
what happens if both A_carry and B_carry for a bit are '0'? The semaforo = '0' and c = '0', that doesn't seem to go along with the intent of finding the max_carry_chain position. It seems to me what you want to do is an XOR/XNOR operation to set/clear the semaforo and use c <= c; when the semaforo is low.

Regards
 

I'm trying to count the maximum number of overs by the sum of two vectors
example
00000010
00011111
the maximum length of carry propagation chain is 4
I need to figure out that only two carriers to be 32-bit
 

So what do you do with something like this?

0000 0000 0000 0011 0000 0000 0001 0000 1st number
0000 0000 1111 1111 1111 0000 1111 1111 2nd number
0000 0000 1111 1111 0000 0000 1111 0000 carry

Is the answer supposed to be 8 or 4 or something else entirely like the bit position of the last carry (23)?
 

The answer in this example must be 8, which is contained in the variable max_carry_chain
 

Then I suggest using a shift operation on the carry, a carry counter, and a register that stores the max carry count for the entire word. Of course this should all be done in a clocked process.

Regards
 

the problem is that I'm not able to scan all 32 bits, but only the first
 

the problem is that I'm not able to scan all 32 bits, but only the first
It's already been explained that it is because you are trying to do the scan as if it was a software program. VHDL is not a programming language it is a hardware description language. Your combinational for loop doesn't represent any type of valid hardware, so of course it simulates incorrectly.

I've given you a conceptual design of how to approach building the scan as a piece of hardware.

Also if you plan on synthesizing the scan code then you better put it in a separate component and instantiate that in your testbench. As it is now you have the scan code embedded in the testbench.


Regards
 

I thought about it, but I'm not able
 

Then design a circuit you do understand. You obviously didn't do any upfront design before pounding on the keyboard.

Some suggested design steps to take before writing code.
1) come up with a block diagram of the design, with major functional blocks to do the operations you want. e.g. carry_generator, adder, max_carry_generator, etc
2) make lower level block diagrams of the circuits that perform the duties of the major functional blocks.
3) figure out how much pipelining you'll need to perform the operations (and meet your timing goals) and come up with pipeline diagram(s) and timing diagram(s).
4) code the design you just did in VHDL following your pipeline diagram(s) and the lower level block diagrams.

And for those that do this for a living like I do, yes I know I'm glossing over a lot of details here...
 
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    FvM

    Points: 2
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I tend to contradict in one point.

Behavioral VHDL code can serve a purpose even if it's no based on a clear idea of intended hardware. In may result in an uneffective implementation or cause problems in synthesis, but that's worth a try and can be at least an instructive experiment.

In any case the code must be aware of HDL syntax and semantic rules, which isn't the case with the present for loop construct. Besides possible other problems it has to use variables to count bits or preserve information during the loop "execution".
 

okay. I almost solved, I made the bitwise operations. Now I find in a string like 001100111000100001100.
How do I calculate the maximum number of consecutive of 1? (code)
 

Since you seem to be incapable of "designing" something...

Here is a block diagram of post #8. Use at your own risk, I just slapped it together (i.e. it might not work and I'm not going to check if it does).
Capture.PNG
FYI, If I don't say so you probably won't add a clock, so... the shift regsiter, carry counter, and max carry count are all sequential (registered) logic. You also have to reset everything when you start up as the max_carry_count and carry_counter will have to both start with 0's.

So now all you have to do is code this circuit and check that it simulates correctly.

Don't forget to credit me with the design, we don't want to end up being expelled for plagiarism. ;-)
 

ads ee,

thanks for your help. It was not a project, but a term paper for an engineering exam. I did 4 adders (ripple carry, carry lookahead, carry-select and square root) and I had to test them with a testbench. I finally finished!
I'll write again on this forum, but this time for the final thesis on code 'code compose'r of texas instruments msp430 microcontroller; also know this language?
 

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