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Sizing of single port 6T SRAM

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Kathan Shah

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I am designing single ported SRAM with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits so muxes would also be required. How do I size each of them? All I know is about sizing 6T cell to minimum so it saves area.
 

that's the job.
 

Do you mean there is no other method except doing smart brute force like sizing? I was thinking of doing some sweep.
 

Look up SRAM butterfly curves. You can't have all the transistors in the 6T cell as minimum.
 
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