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Standard CMOS processes tend to be P- substrate (epi
over P+ handle, when economics support that cost, or
plain bulk P- all the way down for the cheapest wafer).
An N-well is needed for standard voltage PMOS. Its Xj
will be just what is needed to not punch through, the
highest PMOS S/D voltage to the grounded substrate.
Its doping will be low enough that no zener / avalanche
action will occur at max VDD-VSS.
For a P+ region that needs higher voltage, or a NWell that
likewise has to exceed "normal", the well doping will be
brought down and the Xj made deeper. This will let you do
high voltage PMOS, may serve as the drain region for an
extended-drain or LDMOS N-channel, or may house yet
another P- region for floating NMOS (twin well or triple
well).
Every well has a parasitic diode. The deep NWell diode
should have a higher breakdown, a more rounded junction
(also helping BV) due to more side diffusion, possibly lower
leakage (depending on whether impact ionization, or
depletion volume generation current is more significant)
than a standard NWell.
Standard CMOS processes tend to be P- substrate (epi
over P+ handle, when economics support that cost, or
plain bulk P- all the way down for the cheapest wafer).
An N-well is needed for standard voltage PMOS. Its Xj
will be just what is needed to not punch through, the
highest PMOS S/D voltage to the grounded substrate.
Its doping will be low enough that no zener / avalanche
action will occur at max VDD-VSS.
For a P+ region that needs higher voltage, or a NWell that
likewise has to exceed "normal", the well doping will be
brought down and the Xj made deeper. This will let you do
high voltage PMOS, may serve as the drain region for an
extended-drain or LDMOS N-channel, or may house yet
another P- region for floating NMOS (twin well or triple
well).
Every well has a parasitic diode. The deep NWell diode
should have a higher breakdown, a more rounded junction
(also helping BV) due to more side diffusion, possibly lower
leakage (depending on whether impact ionization, or
depletion volume generation current is more significant)
than a standard NWell.
Thanks a lot dick_freebird.
whatever scenarios you explained above, can you please give the cross sectional views and layout(top) view for those scenarios? again deep n well is only used for isolating NMOS s or also w can use deep NWELL for PMOS s as well and if yes then why do we go for deep NWELL instead of simply going for another NWELL. If you are having some cross sectional views and layout views for each case then please share it.
I have attached some images. Please go through it and make me correct if i am wrong.
What you show as "deep N well" is what I would call
a "N+ buried layer". It would indeed improve latchup
somewhat. But it will decrease, not increase, the
NWell-Psub breakdown voltage (which is what I have
seen other deep NWell structures used for - HV devices).
Maybe this is just a nomenclature deal, maybe foundry
specific / dialect. But what I would expect as-named
is a different, deeper well structure, not a highly doped
pocket below the surface.
If its purpose is strapping the bottom of the regular NWell,
doping would be set higher. But if it is to provide a higher
than standard breakdown voltage, doping would be lower.
Lower dopings make a wider depletion region for same voltage,
meaning a lower field against Emax(Si) limit. Or conversely a
junction that can take more voltage before hitting critical
field (provided that there's nothing backstopping the depletion
spread, like the P+ handle below, or S/D implants above).
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